AXI4-Stream Interface

The interface connects a single master to a single slave in a dedicated data flow path. This eliminates bus arbitration logic and shared-medium contention. Key characteristics include:

• No address phases or channels—data flows continuously
• Handshake signals are point-to-point, not broadcast
• Simplifies timing closure in high-speed designs
• Ideal for Direct RF Sampling pipelines where ADC samples stream to a Digital Down Conversion (DDC) core

All data transfers are governed by a two-way handshake using TVALID (master-side) and TREADY (slave-side) signals. A transfer occurs only on a rising clock edge when both are asserted simultaneously.

• TVALID: Master indicates valid data is present on TDATA
• TREADY: Slave indicates it is ready to accept data
• Enables natural back-pressure—slave can stall the pipeline without data loss
• Supports zero-latency throughput when both sides are always ready

The core data payload is carried on TDATA, with critical sideband signals providing packet framing and byte-level granularity:

• TDATA: The primary data bus, typically 8 to 1024 bits wide
• TKEEP: Byte qualifier indicating which bytes of TDATA contain valid data; essential for handling packet residue when data width is not an integer multiple of packet size
• TLAST: Marks the final transfer of a packet or frame, enabling downstream cores to delineate boundaries without parsing payloads
• TID/TDEST: Optional routing identifiers for stream switching fabrics

Unlike the memory-mapped AXI4 variant, AXI4-Stream has no address bus, burst length counters, or transaction IDs for read/write differentiation. This radical simplification yields:

• Minimal logic footprint—no address decoder or transaction state machines
• Deterministic, wire-like latency ideal for Phase Coherency across multiple channels
• Seamless integration with CIC Filters and Polyphase Filter Banks where samples arrive in strict temporal order
• No concept of 'read' or 'write'—only a continuous forward flow

AXI4-Stream natively supports packet-based protocols through the TLAST signal. When TLAST is asserted during a transfer, it marks the end of a logical packet or frame.

• Enables variable-length packet transport without header parsing
• Downstream Decimation Chains can use TLAST to reset filter states at frame boundaries
• Works with TID to interleave multiple logical streams over a single physical interface
• Critical for Pulse Compression engines where each radar pulse is a discrete packet

Modern FPGA design flows using High-Level Synthesis (HLS) map C++ function arguments directly to AXI4-Stream interfaces. The protocol's simple ready/valid semantics map cleanly to:

• hls::stream<> data types in Vitis HLS
• Automatic generation of Ping-Pong Buffer logic for continuous processing
• Direct connection to JESD204C IP cores for multi-gigasample converter interfaces
• Enables software engineers to build Wideband Spectrogram pipelines without hand-coding VHDL/Verilog handshake logic