Inferensys

Glossary

Multi-Rate DPD

A digital predistortion implementation where the predistorter operates at a higher sampling rate than the baseband signal to capture and cancel out-of-band distortion products.
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SAMPLING RATE ARCHITECTURE

What is Multi-Rate DPD?

A digital predistortion architecture where the predistorter operates at a higher sampling rate than the baseband signal to capture and cancel out-of-band distortion products.

Multi-Rate DPD is a digital predistortion implementation where the predistorter operates at a sampling rate significantly higher than the baseband signal's Nyquist rate. This oversampling is essential because the nonlinear predistortion function intentionally expands the signal's bandwidth—typically by a bandwidth expansion factor of 3x to 5x—to generate anti-phase intermodulation distortion (IMD) products that cancel the power amplifier's spectral regrowth in adjacent channels.

The architecture employs interpolation filters to upsample the baseband signal before the predistorter and decimation filters in the observation feedback path. Without multi-rate processing, the predistorted signal would suffer from aliasing distortion, where out-of-band correction components fold back into the desired band, corrupting error vector magnitude (EVM) and rendering adjacent channel leakage ratio (ACLR) improvement ineffective.

ARCHITECTURAL FEATURES

Key Characteristics of Multi-Rate DPD

Multi-Rate Digital Predistortion addresses the fundamental sampling challenge of wideband linearization by operating the predistorter at a higher rate than the baseband signal path. This architecture captures and cancels out-of-band distortion products that would otherwise alias or remain uncompensated.

01

Oversampled Predistorter Path

The core architectural distinction: the predistorter operates at a sampling rate (Fs_DPD) that is an integer multiple of the baseband signal rate (Fs_BB). This oversampling—typically 3x to 5x—is essential because nonlinear distortion expands signal bandwidth. A 100 MHz baseband signal passing through a power amplifier with 5th-order nonlinearity generates distortion products spanning 500 MHz. Without oversampling, these out-of-band components alias back into the Nyquist zone, making them impossible to cancel. The higher-rate path captures the full nonlinear spectrum, synthesizing a predistorted signal with intentional anti-phase distortion across the expanded bandwidth.

3x-5x
Typical Oversampling Ratio
03

Feedback Path Bandwidth Requirements

The observation receiver must digitize the PA output with sufficient bandwidth to capture all distortion products the predistorter aims to cancel. This requires an analog-to-digital converter (ADC) sampling at or above the predistorter rate. For a 200 MHz 5G NR carrier with 5th-order DPD, the feedback ADC must sample at 1 GHz or higher. Key challenges include:

  • ADC effective number of bits (ENOB) degradation at wide bandwidths
  • Anti-aliasing filter design with flat passband and sharp cutoff
  • Jitter-induced noise that limits dynamic range at high input frequencies
  • Feedback path linearization to prevent the observation receiver itself from introducing uncompensated distortion
>1 GHz
Feedback ADC Rate for 5G Wideband
04

Aliasing Management in Coefficient Estimation

Coefficient estimation algorithms in multi-rate DPD must explicitly account for aliased distortion products. When the feedback ADC rate is lower than the full nonlinear bandwidth, out-of-band distortion folds into the observed spectrum. The indirect learning architecture adapts by:

  • Band-limiting the model output to match the feedback bandwidth before error calculation
  • Spectral extrapolation using the behavioral model to predict unobservable distortion
  • Frequency-selective training that weights in-band and adjacent-channel errors differently

Failure to manage aliasing leads to coefficient bias—the predistorter optimizes for the aliased spectrum rather than the true PA output, degrading ACLR performance.

05

Computational Complexity vs. Linearization Depth

Multi-rate DPD introduces a complexity tradeoff between the oversampling factor and achievable linearization. Higher rates enable cancellation of higher-order intermodulation products but increase:

  • Multiply-accumulate operations scaling with the predistorter sample rate
  • Coefficient memory for models with memory depth (e.g., memory polynomial with M taps)
  • Feedback path power consumption from high-speed ADCs
  • Latency through interpolation and decimation filter chains

Practical implementations balance these factors. A 3x oversampled DPD typically captures 3rd and 5th-order distortion adequately for ACLR compliance, while 5x may be necessary for stringent spectral masks or when compensating 7th-order nonlinearities in GaN PAs.

3x-5x
Practical Oversampling Range
06

Decimation in the Adaptation Loop

The coefficient estimation path operates at a reduced rate compared to the predistorter to minimize computational load. After capturing the wideband feedback signal, a decimation chain reduces the sample rate before model extraction. This is valid because:

  • Coefficient adaptation converges slowly relative to the signal dynamics
  • Stochastic gradient methods tolerate subsampled error signals
  • Correlation-based estimation (e.g., least squares) can operate on decimated data blocks

The decimation factor must preserve the distortion bandwidth of interest. Aggressive decimation that aliases adjacent-channel energy into the estimation band will produce biased coefficients that fail to suppress spectral regrowth.

MULTI-RATE DPD

Frequently Asked Questions

Clear, technical answers to the most common questions about multi-rate digital predistortion architectures, sampling rate trade-offs, and wideband linearization implementation.

Multi-rate digital predistortion (DPD) is an implementation architecture where the predistorter operates at a higher sampling rate than the baseband signal generation path to capture and cancel out-of-band distortion products. The core mechanism involves upsampling the baseband signal before the predistorter, applying the nonlinear correction at this elevated rate, and then feeding the result to the digital-to-analog converter (DAC). This rate increase is essential because power amplifier nonlinearity generates spectral regrowth that extends well beyond the original signal bandwidth—often by a factor of 3x to 5x. Without oversampling, the predistorter cannot synthesize the inverse intermodulation products needed to cancel adjacent channel leakage. The architecture typically employs a bandwidth expansion factor that dictates the minimum required predistortion sampling rate relative to the signal bandwidth.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.