GaN Trapping

Electrons become captured at dangling bonds and surface donor states on the AlGaN/GaN interface, particularly in the gate-drain access region. This creates a virtual gate effect that depletes the 2DEG channel.

• Mechanism: High electric fields inject electrons into surface traps during large-signal operation
• Impact: Causes current collapse—a temporary reduction in drain current following high-voltage stress
• Recovery: Trap emission occurs over microsecond to millisecond timescales, creating slow transient responses
• Mitigation: Surface passivation with SiN or AlN layers reduces trap density

Deep-level traps in the Fe-doped or C-doped buffer layers capture electrons injected from the channel under high-field conditions. This is distinct from surface trapping and occurs deeper within the epitaxial structure.

• Origin: Intentional doping with iron or carbon creates deep acceptor states for semi-insulating behavior
• Activation: Hot electrons gain sufficient energy to overcome the channel-buffer barrier
• Consequence: Creates a back-gating effect that modulates threshold voltage dynamically
• Thermal Coupling: Trap emission is strongly temperature-dependent, linking buffer trapping to self-heating effects

Two distinct transient phenomena characterize GaN trapping dynamics, differentiated by the terminal experiencing the voltage stress.

• Gate-Lag: A slow recovery of drain current following a gate voltage pulse. Caused primarily by surface traps under the gate edge responding to changes in gate bias
• Drain-Lag: A slow recovery following a drain voltage pulse. Caused by buffer traps and surface traps in the gate-drain region responding to high electric fields
• Characterization: Pulsed I-V measurements with varying quiescent bias points isolate these effects
• DPD Relevance: Both phenomena create history-dependent nonlinearity that memoryless predistorters cannot correct

Trapping and self-heating are coupled phenomena in GaN HEMTs. Elevated junction temperature accelerates trap emission, while trapped charge alters the electric field distribution and thus the power dissipation profile.

• Thermally-Activated Emission: Trap time constants decrease exponentially with temperature following Arrhenius behavior
• Competing Effects: Self-heating reduces current collapse by promoting detrapping, but also degrades mobility
• Modeling Challenge: Requires electro-thermal-trap co-simulation to capture the full dynamic behavior
• DPD Implication: Thermal-aware predistorters must account for this coupling to maintain linearity across temperature ranges

A specific manifestation of buffer trapping where the knee voltage—the transition point between linear and saturation regions—shifts dynamically under large-signal operation.

• Physical Origin: Trapped negative charge in the buffer increases the effective channel resistance
• Efficiency Impact: Increased knee voltage raises the minimum drain voltage for saturation, reducing power-added efficiency (PAE)
• Waveform Engineering: Requires dynamic load modulation to maintain efficiency as knee voltage shifts
• Measurement: Observed through pulsed I-V curves with varying quiescent drain bias stress conditions

Accurate DPD requires behavioral models that capture trapping dynamics alongside thermal memory. Several modeling approaches address this challenge.

• Augmented Memory Polynomial: Adds trap-state variables to standard memory polynomial structures to model slow charge capture and emission
• Two-Box Models: Cascade a trap dynamics block (capture/emission rates) with a conventional nonlinearity block
• State-Space Formulations: Represent trap occupancy as hidden state variables evolving with input envelope history
• Neural Network Approaches: RNNs and LSTMs naturally capture the long-term dependencies characteristic of trapping transients

A primary trapping mechanism where electrons are captured by defect states at the semiconductor-passivation interface. This creates a virtual gate that depletes the channel, causing current collapse and dynamic on-resistance. Unlike thermal effects, surface trapping has a wide distribution of time constants, from nanoseconds to seconds, making it a dominant contributor to slow memory effects in GaN HEMTs.

A phenomenon where electrons are injected from the 2DEG channel into deep-level traps within the Fe- or C-doped buffer layer under high drain bias. This trapped charge depletes the channel from the backside, causing a temporary reduction in drain current. Key characteristics include:

• Bias-dependent time constants that scale with electric field
• Strong interaction with self-heating due to thermally activated emission
• Requires gate-lag and drain-lag characterization to isolate

A pulsed I-V measurement technique used to quantify trapping dynamics. The gate voltage is pulsed from an off-state quiescent point to an on-state while the drain is held at low voltage. The transient recovery of drain current reveals the emission time constants of traps under the gate region. Gate-lag is particularly sensitive to surface traps and barrier layer defects.

A pulsed measurement where the drain voltage is switched from a high-voltage off-state to a lower-voltage on-state. The slow recovery of drain current exposes traps in the buffer layer and access regions. Drain-lag is strongly thermally activated, with time constants decreasing at elevated temperatures. This technique is essential for separating buffer trapping from surface effects.

Advanced compact models like the ASM-HEMT and MVSG incorporate trap dynamics through:

• SRH recombination statistics for capture/emission rates
• Distributed RC networks to model dispersive effects
• State variables that track trapped charge density These physics-based models enable circuit simulations that predict dynamic current collapse under modulated RF signals, critical for DPD algorithm validation.

In hard-switching power converters, GaN HEMTs exhibit a transient increase in on-resistance immediately after turn-on due to hot-electron trapping during the high-voltage off-state. This dynamic RDS(on) degrades converter efficiency and is a key reliability concern. Mitigation strategies include:

• Optimized gate drive with negative off-state voltage
• Proprietary hole-injection techniques to neutralize trapped charge
• Device-level engineering of the buffer stack