Inference Latency

The total number of multiply-accumulate operations (MACs) directly dictates the minimum theoretical latency. A deep augmented memory polynomial network with hundreds of coefficients requires significantly more cycles than a shallow cascade forward network. Complexity is driven by:

• Number of hidden layers and neurons per layer
• Inclusion of cross-terms and envelope-dependent branches
• Activation function computation (e.g., tanh vs. ReLU)
• Complex-valued vs. real-valued arithmetic paths

Latency is not just about total operations but how they map to silicon. FPGA-based DPD implementations exploit massive parallelism by unrolling the neural network into a deeply pipelined datapath. Key techniques include:

• Systolic array architectures for matrix-vector multiplication
• Look-up table (LUT) based activation functions to avoid transcendental math
• Retiming registers to minimize critical path delay between pipeline stages
• Direct DSP slice mapping for multiply-accumulate chains

The bit-width of weights and activations creates a direct trade-off between linearization accuracy and inference speed. Post-training quantization reduces 32-bit floating-point parameters to fixed-point representations:

• INT8 quantization halves memory bandwidth and doubles MAC throughput
• Power-of-two quantization replaces multipliers with bit-shifts
• Aggressive INT4 or binary neural networks minimize logic depth
• Quantization-aware training (QAT) recovers accuracy lost during precision reduction

The tapped delay line structure inherent to memory polynomial and RVTDNN models requires accessing past input samples. Memory subsystem design impacts latency through:

• Shift register implementation for deterministic, single-cycle access to delayed samples
• On-chip block RAM (BRAM) vs. distributed RAM trade-offs
• Avoiding off-chip DDR memory accesses which introduce non-deterministic latency
• Coefficient storage layout optimized for vectorized fetch

The Nyquist sampling rate for the predistorted signal sets the absolute time budget per inference. A 100 MHz wideband 5G NR carrier requires a sample period of just a few nanoseconds, forcing the entire neural network forward pass to complete within this window. Wider bandwidths demand:

• Simpler model architectures with fewer sequential operations
• Higher degrees of hardware parallelism
• Careful management of spectral regrowth compensation bandwidth (typically 3-5x the signal bandwidth)

Nonlinear activation functions like tanh and sigmoid are latency bottlenecks due to their transcendental math. Hardware-friendly alternatives include:

• Piecewise linear (PWL) approximations using comparators and multiplexers
• Look-up table (LUT) based evaluation with linear interpolation
• ReLU and leaky ReLU for zero-cost thresholding
• Spline interpolation nodes that double as both activation and PA nonlinearity model

The process of reducing the numerical precision of a neural network's weights and activations from 32-bit floating-point (FP32) to lower bit-width integers like INT8 or INT4. This directly reduces inference latency by replacing expensive floating-point multiply-accumulate operations with faster, lower-power integer arithmetic on FPGA or ASIC hardware. Quantization-aware training (QAT) simulates quantization noise during the training loop to recover accuracy lost by post-training quantization (PTQ).

A model compression technique that removes redundant or low-magnitude weights from a trained predistorter network to create a sparse computational graph. By eliminating near-zero parameters, pruning reduces the total number of operations required per inference pass, directly lowering latency.

• Unstructured pruning: Zeroes out individual weights, creating irregular sparsity.
• Structured pruning: Removes entire neurons, filters, or channels, yielding hardware-friendly regular sparsity patterns that map efficiently to parallel compute units.

The hardware acceleration of digital predistortion algorithms on Field-Programmable Gate Arrays (FPGAs) or Application-Specific Integrated Circuits (ASICs). FPGAs enable deterministic, ultra-low inference latency through massively parallel, pipelined datapaths. Key implementation considerations include:

• Pipelining: Overlapping computation stages to maximize throughput.
• Resource utilization: Balancing DSP slices, block RAM, and logic fabric.
• Latency budgeting: Ensuring the total compute path fits within the strict timing window between sample arrival and transmission.

An adaptive training paradigm where the neural network predistorter coefficients are continuously updated during live signal transmission to track time-varying PA characteristics. Unlike offline training with fixed inference latency, online learning introduces a dynamic trade-off: the system must balance the computational overhead of coefficient updates against the real-time deadline of sample-by-sample predistortion. Background update threads and incremental learning algorithms are used to avoid interrupting the inference pipeline.

A feedforward neural network that uses tapped delay lines on real-valued I/Q signal components to model PA memory effects. The RVTDNN's inference latency is a function of its depth (number of hidden layers), width (neurons per layer), and the length of the tapped delay line. Its relatively simple feedforward structure makes it a popular choice for hardware implementation where the inference time must be strictly bounded and predictable, unlike recurrent architectures that may have variable-length computation graphs.

The ability of a trained neural network predistorter to maintain linearization performance across varying signal bandwidths, power levels, and environmental conditions not seen during training. A model that overfits to a specific training signal may exhibit low inference latency but fail catastrophically on new waveforms. Generalization is directly at odds with aggressive latency-reduction techniques like pruning and quantization, which can strip the network of the representational capacity needed to handle diverse operating conditions.