Trapping Effects

Deep-level traps in the semiconductor bandgap capture free electrons from the channel during high-power operation. These trap states originate from crystal defects, dislocations, and surface states at the passivation interface. The capture time constant ranges from microseconds to milliseconds, creating a gate-lag or drain-lag phenomenon where the instantaneous drain current depends on the prior signal envelope history.

Two distinct manifestations of trapping:

• Gate-Lag: Electron capture under the gate contact during high VGS, causing slow current recovery when switching to lower VGS. Dominant in pulsed operation.
• Drain-Lag: Electron capture in the gate-drain access region under high VDS stress, causing current collapse that recovers with millisecond-scale time constants. Both effects create hysteresis in I-V characteristics that static models cannot capture.

Trapping introduces long-term memory effects that extend beyond the temporal span of conventional memory polynomial models. Key consequences for linearization:

• AM-AM and AM-PM curves become history-dependent, varying with average power and duty cycle
• Standard GMP models with 3-5 memory taps fail to capture millisecond-scale trap dynamics
• Coefficient drift occurs as trap occupancy changes during transmission bursts
• Requires augmented DPD models with envelope-dependent terms or recurrent neural network structures

In GaN HEMTs, trapping originates from multiple physical locations:

• Buffer traps: Iron or carbon doping in the GaN buffer creates deep acceptors that capture electrons from the 2DEG channel
• Surface traps: Unpassivated AlGaN surface states between gate and drain act as virtual gates, depleting the channel
• Interface traps: Defects at the AlGaN/GaN heterointerface modulate 2DEG density
• Passivation quality directly determines surface trap density and current collapse severity

Specialized measurement methods isolate trapping from thermal effects:

• Pulsed I-V: Short-duration pulses (200 ns - 1 μs) from multiple quiescent bias points reveal trap-induced knee voltage walkout and current collapse
• Double-pulse testing: Two consecutive pulses with varying inter-pulse delay measure trap capture/emission time constants
• Low-frequency dispersion: S-parameter measurements below 1 MHz reveal trap-related transconductance frequency dispersion
• Drain current transient spectroscopy: Time-domain current recovery after bias switching extracts trap energy levels and capture cross-sections

Approaches to reduce trapping effects in DPD systems:

• Device-level: Optimized field plate designs, improved passivation (SiN, AlN), and buffer engineering reduce trap density
• Circuit-level: Envelope tracking and dynamic bias control maintain channel conditions that minimize trap occupancy variation
• Algorithm-level: LSTM-based DPD and ARVTDNN architectures learn trap dynamics from waveform history; coefficient interpolation across power levels compensates for trap-state dependence on average operating point

The two primary observable manifestations of trapping effects. Gate lag refers to the slow transient response of drain current following a change in gate-source voltage, caused by surface traps between gate and drain. Drain lag describes the slow drain current recovery after a drain voltage pulse, attributed to buffer traps in the epitaxial layers or bulk substrate. Both introduce bias-history-dependent dispersion that complicates linearization.

Techniques for isolating trapping dynamics from self-heating. Iso-thermal pulsed I-V measurements use short pulses (typically 200 ns–1 µs) with long quiescent periods to maintain constant channel temperature while varying bias points. By comparing pulsed I-V curves at different quiescent bias conditions, engineers can separate surface trapping from buffer trapping contributions and extract trap time constants for model parameterization.

The physical mechanism governing trapping dynamics, described by Shockley-Read-Hall (SRH) recombination statistics. Key parameters include:

• Capture cross-section (σ): Probability of a carrier being captured by a trap, typically 10⁻¹²–10⁻¹⁵ cm²
• Activation energy (Eₐ): Energy barrier for carrier emission, determining temperature dependence
• Trap density (Nₜ): Concentration of active trap states, often 10¹³–10¹⁴ cm⁻³ in GaN HEMTs These parameters define the exponential time constants observed in gate and drain lag.

A critical distinction in behavioral modeling. Short-term memory effects (ns–µs range) arise from impedance matching networks, bias circuit decoupling, and carrier transit time. Long-term memory effects (µs–s range) are dominated by trapping and self-heating. Trapping-induced long-term memory causes the amplifier's nonlinear behavior to depend on the signal envelope history over extended periods, requiring models with deep temporal context such as LSTM-DPD or Augmented GMP structures.

Device-level mitigation strategies for trapping effects in GaN HEMTs:

• SiN passivation: Silicon nitride layers deposited on the AlGaN surface reduce surface state density and suppress gate lag
• Field plates: Gate-connected or source-connected field plates redistribute the peak electric field, reducing electron injection into surface traps
• Carbon doping optimization: Careful control of carbon doping in the GaN buffer layer minimizes drain lag while maintaining breakdown voltage These techniques reduce, but do not eliminate, the need for DPD compensation.

The DDR-Volterra model is particularly effective for trapping effects because it explicitly separates static nonlinearity from low-order dynamic deviations. By limiting the dynamic order to 1 or 2, DDR captures the slow-varying envelope-dependent behavior of traps without the combinatorial explosion of full Volterra kernels. This makes it suitable for wideband mmWave DPD where trapping memory spans many symbol periods.