Direct RF Sampling

By connecting the antenna directly to the Analog-to-Digital Converter (ADC) via only a low-noise amplifier and anti-aliasing filter, the architecture removes local oscillators, mixers, and I/Q modulators. This avoids LO leakage, I/Q imbalance, and flicker noise that plague zero-IF receivers. The result is a perfectly orthogonal I/Q representation defined mathematically in the digital domain, enabling more accurate wideband DPD coefficient extraction.

Direct RF sampling leverages undersampling or bandpass sampling to intentionally alias a high-frequency signal into a lower Nyquist zone. The ADC sample rate (fs) must satisfy fs > 2×B (where B is the instantaneous bandwidth), not 2× the carrier frequency. This allows digitization of mmWave signals with ADCs running at rates far below the carrier, provided the sample-and-hold amplifier (SHA) has sufficient analog input bandwidth and aperture jitter performance.

The primary performance limiter is aperture jitter—the sample-to-sample timing uncertainty in the ADC clock. This jitter convolves with the high-slew-rate RF carrier to raise the integrated noise floor. The theoretical Signal-to-Noise Ratio (SNR) degradation follows: SNR_jitter = -20 × log10(2π × f_in × t_jitter). For mmWave frequencies, this demands ultra-low phase noise clock sources with femtosecond-level jitter to preserve the dynamic range needed for DPD observation.

Capturing the full 100 MHz to 2 GHz instantaneous bandwidth required for 5G NR and future systems is only feasible with direct sampling. The architecture observes not just the in-band distortion but also the adjacent channel spectral regrowth and harmonic distortion in a single coherent capture. This wideband visibility is critical for training neural network DPD models that must linearize across the entire transmit band and cancel cross-band modulation products in multi-band scenarios.

Modern RF System-on-Chip (RFSoC) devices from vendors like AMD-Xilinx integrate multi-GSPS ADCs, DACs, and FPGA fabric on a single die. This monolithic integration minimizes digital I/O power and latency between the data converters and the DPD processing engine. The tight coupling enables real-time closed-loop DPD with deterministic latency, where the predistorted signal is generated and the amplifier output is observed within the same clock domain, critical for adaptive tracking.

In undersampled systems, wideband noise and harmonics from the ADC's own track-and-hold circuit and front-end can fold back into the band of interest. Rigorous frequency planning is required to ensure that no high-order harmonics of the sampling clock or the digitized signal alias onto the desired carrier. This involves selecting a sample rate that places the signal in a clean Nyquist zone and using high-linearity buffer amplifiers to prevent out-of-band energy from contaminating the in-band spectrum.

An integrated semiconductor device that combines high-speed ADCs and DACs with FPGA fabric and processing cores on a single die. RFSoCs are the primary enabler of direct RF sampling, eliminating discrete data converter interfaces and dramatically reducing system power and footprint.

• Integrates multi-GSPS converters directly with programmable logic
• Eliminates JESD204B/C interfaces between discrete components
• Enables real-time DPD processing at the antenna for massive MIMO arrays

A technique where the ADC intentionally samples a signal in a higher Nyquist zone (beyond fs/2), using the aliasing property of sampling to downconvert the RF signal to baseband without analog mixers. This exploits the ADC's input bandwidth to directly capture signals at carrier frequencies well above the sample rate.

• Requires careful anti-alias filtering to isolate the desired zone
• Leverages ADC track-and-hold bandwidth rather than sample rate
• Common in mmWave systems where ADCs cannot sample at twice the carrier

The removal of high-speed serial data converter interfaces that traditionally connect discrete ADCs to FPGAs. Direct RF sampling with RFSoCs eliminates these multi-gigabit transceiver links, reducing latency, PCB complexity, and deterministic jitter that degrades DPD linearization performance.

• Removes lane alignment and deterministic latency management overhead
• Reduces feedback path delay, critical for wideband DPD convergence
• Simplifies multi-channel synchronization for phased array systems

The requirement that the observation receiver chain used for DPD training must be significantly more linear than the PA under correction. In direct RF sampling, the ADC's inherent linearity and the absence of mixer-generated intermodulation products provide a cleaner feedback reference, improving coefficient estimation accuracy.

• Eliminates mixer IP3 and LO leakage from the observation path
• ADC SFDR directly determines observable distortion floor
• Critical for achieving -60 dBc ACLR targets in 5G NR systems

The process of digitally mixing, filtering, and decimating the high-rate ADC output to extract the band of interest. Unlike analog down-conversion, DDC is performed entirely in the FPGA fabric using numerically controlled oscillators (NCOs) and cascaded integrator-comb (CIC) filters, providing perfect I/Q balance and programmable bandwidth.

• Enables flexible carrier frequency selection without hardware changes
• Eliminates I/Q imbalance inherent in analog quadrature demodulators
• Supports multi-carrier extraction from a single wideband data stream

The precision synchronization of transmitted and observed waveforms to within a fraction of a sample period using fractional delay filters. Direct RF sampling's deterministic latency simplifies loop delay estimation, but wideband DPD still requires sub-sample accuracy to properly align high-frequency distortion components.

• Farrow structure filters provide continuously variable fractional delay
• Misalignment of 0.1 samples can degrade DPD correction by several dB
• Critical for capturing memory effects in wideband signals