Digital Predistortion (DPD)

DPD operates by applying a nonlinear inverse function to the signal before it enters the power amplifier (PA). If the PA exhibits gain compression (AM-AM distortion) and phase shift (AM-PM conversion), the DPD engine expands the signal and applies an opposing phase rotation. The cascade of the predistorter and the PA ideally results in a linear system with constant gain and zero phase offset up to saturation.

• Goal: Achieve a perfectly linear output where the output is a scalar multiple of the input.
• Mechanism: The predistorter's transfer function is the mathematical inverse of the PA's complex gain.

Unlike static analog linearizers, DPD is an adaptive digital system. It continuously monitors the PA output via a feedback observation receiver. Changes in PA behavior due to temperature drift, aging, or antenna load mismatch (VSWR) are detected, and the predistorter coefficients are updated in real-time.

• Architecture: Typically uses an Indirect Learning Architecture (ILA) or Direct Learning Architecture (DLA).
• Benefit: Maintains spectral mask compliance and EVM performance over the entire product lifecycle without manual recalibration.

Modern DPD engines do not just correct static nonlinearity; they compensate for memory effects. These are dynamic distortions where the PA's output depends on current and previous input samples.

• Short-term (Electrical) Memory: Caused by bias circuit impedances and matching network frequency response. Corrected using tapped delay lines or memory polynomials.
• Long-term (Thermal) Memory: Caused by self-heating and die temperature fluctuations. Corrected using models that incorporate low-frequency envelope terms.
• Trapping Effects: Specific to GaN devices, these slow charge/discharge phenomena require specialized long-memory models.

DPD is implemented entirely in the digital baseband domain before the digital-to-analog converter (DAC). The complex baseband I/Q samples are manipulated mathematically.

• Implementation: Executed on an FPGA, ASIC, or RFSoC using a hardware-accelerated predistorter block.
• Signal Path: Baseband I/Q → DPD Engine → DAC → IQ Modulator → PA.
• Advantage: Allows for precise, repeatable, and complex mathematical transformations that are impossible to achieve with analog components.

The core of DPD is a behavioral model that accurately describes the PA's nonlinear dynamics. The accuracy of the linearization is directly tied to the fidelity of this model.

• Volterra Series: The most general model, but computationally complex. Pruned versions like the Generalized Memory Polynomial (GMP) and Dynamic Deviation Reduction (DDR) are used in practice.
• Neural Networks: Modern approaches use Real-Valued Time-Delay Neural Networks (RVTDNN) or Convolutional Neural Networks (CNN-DPD) to automatically learn complex features without explicit polynomial basis functions.

To effectively cancel distortion, the DPD engine must process a signal bandwidth that is 3x to 5x wider than the original transmission signal. Nonlinearities generate spectral regrowth (intermodulation products) that spread into adjacent channels.

• Requirement: The DPD signal path (DAC, modulator, and feedback ADC) must support this expanded bandwidth.
• Challenge: For a 100 MHz 5G NR carrier, the DPD system may need to operate at 500 MHz of instantaneous bandwidth, demanding very high-speed data converters and processing logic.