Memory depth is the integer parameter M that defines the number of tapped delay line elements in a memory polynomial or Volterra-based predistorter model. It specifies how many prior complex baseband samples—from x(n-1) to x(n-M)—are included alongside the current sample x(n) to capture the power amplifier's memory effects, such as thermal trapping, bias circuit modulation, and semiconductor charge storage. A depth of zero corresponds to a memoryless nonlinearity.
Glossary
Memory Depth

What is Memory Depth?
Memory depth defines the temporal span of a behavioral model, specifying the number of past input samples used to predict a power amplifier's current nonlinear output.
Selecting optimal memory depth involves balancing linearization accuracy against computational complexity. Insufficient depth fails to suppress memory-induced spectral asymmetry, while excessive depth introduces redundant coefficients that degrade numerical conditioning and increase FPGA resource utilization. The required depth scales with signal bandwidth relative to the amplifier's memory time constant, with wideband 5G signals typically demanding larger M values than narrowband LTE carriers.
Key Factors Influencing Optimal Memory Depth
Selecting the correct memory depth is a critical design decision that balances linearization accuracy against computational complexity. The optimal value is not universal but depends on the specific power amplifier technology, signal bandwidth, and operating conditions.
Amplifier Semiconductor Technology
The physical construction of the transistor dictates the duration and nature of memory effects.
- Gallium Nitride (GaN): Exhibits significant charge-trapping effects requiring deeper memory (often 5-7 taps) to model long-term transient behaviors.
- Laterally-Diffused Metal-Oxide Semiconductor (LDMOS): Dominated by shorter-term thermal memory; typically requires moderate depth (3-5 taps).
- Gallium Arsenide (GaAs): Generally has weaker memory effects, often adequately modeled with shallow depth (2-3 taps).
Signal Bandwidth and Sample Rate
Memory depth must span the physical duration of the amplifier's impulse response, not just a fixed number of samples.
- Wideband signals (e.g., 100 MHz for 5G NR) have short symbol periods. A depth of 4 taps covers only 40 ns, which may miss long-term thermal effects lasting microseconds.
- Narrowband signals (e.g., 5 MHz LTE) have longer symbol periods. The same 4-tap depth covers 800 ns, capturing a much longer physical memory span.
- Rule of thumb: The temporal span (Memory Depth / Sample Rate) must exceed the slowest thermal time constant of the amplifier.
Computational Complexity Budget
Each additional memory tap multiplies the number of basis functions and coefficients in the model.
- For a Generalized Memory Polynomial (GMP) with nonlinear order K and memory depth M, the coefficient count scales with M × K.
- Doubling memory depth from 3 to 6 can quadruple the number of cross-terms in a full GMP model.
- FPGA resource impact: Each complex multiply-accumulate (CMAC) operation consumes DSP slices. Deeper memory directly increases logic utilization and power consumption, potentially violating timing closure.
Numerical Conditioning and Stability
Excessive memory depth introduces highly correlated basis functions, degrading the condition number of the data matrix.
- Ill-conditioned matrices lead to coefficient estimation instability, where small measurement noise causes large coefficient variance.
- This manifests as overfitting: the model memorizes training data noise rather than learning the true amplifier physics.
- Mitigation requires regularization (e.g., Ridge regression) or basis function orthogonalization, adding further computational overhead.
Thermal Time Constants
Power amplifiers exhibit both short-term and long-term thermal memory effects that dictate minimum required depth.
- Short-term (die-level): Microsecond-scale heating at the transistor junction. Captured by shallow memory (2-4 taps at typical sample rates).
- Long-term (package-level): Millisecond-scale thermal diffusion through the substrate and heat sink. Requires very deep memory or a separate envelope memory polynomial structure.
- Ignoring long-term thermal memory causes drift in linearization performance during sustained transmission bursts.
Model Extraction Methodology
The chosen memory depth must be validated against measured data, not assumed.
- Sweep depth systematically: Train models with M = 1, 2, 3, ... taps and measure Normalized Mean Squared Error (NMSE) on a held-out test set.
- Diminishing returns point: The depth at which adding another tap improves NMSE by less than 0.5 dB is the practical optimum.
- Cross-validation prevents selecting a depth that overfits the specific training signal statistics.
Memory Depth vs. Related Model Parameters
Comparison of memory depth against nonlinear order, coefficient count, and computational cost across common behavioral model structures.
| Parameter | Memory Polynomial (MP) | Generalized Memory Polynomial (GMP) | Volterra Series (Truncated) |
|---|---|---|---|
Memory Depth (M) | 3–7 taps | 3–7 taps | 2–5 taps |
Nonlinear Order (K) | 5–11 | 5–9 | 3–7 |
Coefficient Count | M × K | M × K + cross-terms | Exponential in M and K |
Cross-Term Memory Span | |||
Envelope Memory Terms | |||
Numerical Conditioning | Good | Moderate | Poor |
FPGA Resource Utilization | Low | Medium | High |
Linearization Performance (ACPR Improvement) | 15–20 dB | 18–25 dB | 20–30 dB |
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Frequently Asked Questions
Explore the critical role of memory depth in power amplifier behavioral modeling and digital predistortion. These answers clarify how temporal history shapes linearization accuracy and computational complexity.
Memory depth defines the number of past input samples used in a model with memory, establishing the temporal span over which the power amplifier's history influences its current output. In digital predistortion, this parameter directly determines how many tapped delay lines are incorporated into structures like the Memory Polynomial (MP) or Generalized Memory Polynomial (GMP). A memory depth of M means the model considers the current input sample plus M-1 previous samples. This captures long-term thermal effects, bias circuit relaxation, and trapping phenomena in GaN/GaAs amplifiers that cannot be modeled by memoryless nonlinearities alone. Selecting the correct depth is a trade-off: too shallow, and residual memory effects degrade Adjacent Channel Power Ratio (ACPR); too deep, and the coefficient vector becomes unnecessarily large, increasing FPGA resource utilization and slowing Recursive Least Squares (RLS) convergence.
Related Terms
Understanding memory depth requires familiarity with the model structures, estimation algorithms, and complexity management techniques that define the temporal span of power amplifier behavioral models.
Memory Polynomial (MP) Model
The foundational behavioral model that introduces memory depth as a core parameter. It uses a polynomial with tapped delay lines to capture both nonlinear distortion and memory effects.
- Structure: A sum of polynomials applied to delayed input samples
- Key parameter: M (memory depth) defines the number of past samples
- Complexity scales as O(K × M) where K is nonlinear order
- Serves as the baseline against which more complex models are compared
Generalized Memory Polynomial (GMP)
An enhanced model that extends the memory polynomial by including cross-terms between the signal and its lagging or leading envelope samples.
- Introduces lagging cross-terms: |x(n-l)|² · x(n-m)
- Introduces leading cross-terms: |x(n+l)|² · x(n-m)
- Captures complex memory effects missed by standard MP
- Memory depth applies to both signal and envelope dimensions
Volterra Kernel Pruning
A complexity reduction technique that removes insignificant kernels from a full Volterra series based on a significance metric. Memory depth directly determines the number of kernels that must be evaluated and pruned.
- Full Volterra kernels grow exponentially with memory depth
- Pruning retains only the most critical distortion terms
- Common metrics: kernel magnitude, correlation with output error
- Essential for making high-memory-depth models practical
Recursive Least Squares (RLS) Estimation
An adaptive filtering algorithm that recursively updates predistorter coefficients as memory depth changes. The forgetting factor λ controls how quickly old data is discounted.
- Convergence speed is affected by memory depth dimensionality
- Larger memory depth → larger covariance matrix → slower updates
- RLS complexity: O(N²) where N = number of coefficients
- Often paired with orthogonalization to improve conditioning
Model Order Reduction
The systematic process of decreasing the number of coefficients in a behavioral model while preserving linearization performance. Memory depth is a primary target for reduction.
- Techniques include Orthogonal Matching Pursuit (OMP) and PCA
- Goal: minimize memory depth without degrading ACPR improvement
- Critical for FPGA implementations with limited DSP slices
- Trade-off: reduced memory depth vs. residual nonlinearity
Envelope Memory Polynomial
A model variant that incorporates memory effects of the signal's envelope magnitude rather than just the complex baseband samples. This captures long-term thermal and bias-related memory.
- Envelope memory depth is typically longer than signal memory depth
- Captures slow-varying effects: thermal time constants, bias modulation
- Structure: combines standard MP terms with envelope-dependent terms
- Particularly important for GaN and Doherty amplifiers

About the author
Prasad Kumkar
CEO & MD, Inference Systems
Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.
His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.
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