Look-Up Table (LUT) Indexing

The instantaneous envelope magnitude |x(n)| of the complex baseband input signal serves as the direct index into the LUT. This one-dimensional mapping eliminates complex address calculations:

• Uniform spacing: Table entries are evenly distributed across the input magnitude range
• Non-uniform spacing: Entries are concentrated in regions of rapid gain variation (e.g., compression knee) for improved resolution
• Address calculation: Index = floor(|x(n)| / step_size) for uniform tables

The magnitude-only addressing scheme assumes the PA's nonlinearity is memoryless and depends solely on instantaneous input power, making it suitable for narrowband applications where memory effects are negligible.

Each LUT entry stores a complex-valued gain correction factor G(|x|) = G_I + jG_Q that multiplies the input sample to produce the predistorted output:

• Gain magnitude: Compensates for AM-AM distortion (gain compression/expansion)
• Gain phase: Compensates for AM-PM distortion (phase shift vs. input power)
• Storage format: Typically 16-32 bits for I and Q components in fixed-point FPGA implementations

The predistorted output is computed as: y(n) = x(n) × G(|x(n)|) where G is retrieved from the table at the index corresponding to |x(n)|.

To avoid quantization artifacts from finite table resolution, interpolation smooths the transition between adjacent LUT entries:

• Linear interpolation: Computes G as a weighted average of two neighboring entries based on the fractional address
• Cubic interpolation: Uses four neighboring points for smoother correction, at higher computational cost
• No interpolation: Direct nearest-neighbor lookup, fastest but introduces stair-step distortion

Interpolation significantly reduces quantization noise in the predistorted signal, improving ACLR by 3-5 dB compared to un-interpolated lookup at the same table size.

The number of LUT entries directly impacts both linearization performance and hardware resource utilization:

• Small tables (64-128 entries): Minimal BRAM usage, faster adaptation, but coarser correction
• Medium tables (256-512 entries): Good balance for most narrowband applications
• Large tables (1024+ entries): Finer gain resolution, better ACLR, but increased memory footprint and slower coefficient updates

Typical FPGA implementations use 256-512 entries with linear interpolation, achieving ACLR improvements of 15-20 dB for memoryless PA characteristics while consuming minimal block RAM resources.

LUT coefficients must adapt to track PA characteristic drift due to temperature, aging, and frequency changes:

• Direct learning: Compares PA output to desired linear output, updates LUT entries using LMS or RLS algorithms
• Indirect learning: First identifies PA model, then inverts it to populate the LUT
• Selective updating: Only entries that were recently addressed are updated, reducing computation
• Gain-based update rule: G_new = G_old - μ × e(n) × x*(n) / |x(n)|² where e(n) is the linearization error

Adaptation convergence time depends on the step size μ and signal statistics, typically requiring 10³-10⁴ samples per entry for stable convergence.

LUT indexing assumes a memoryless nonlinearity, which breaks down for wideband signals where PA memory effects become significant:

• Bandwidth threshold: Memory effects become non-negligible when signal bandwidth exceeds ~1% of the carrier frequency
• Spectral regrowth asymmetry: Memoryless LUT cannot correct asymmetric IMD skirts caused by electrical and thermal memory
• Mitigation approaches: Combine LUT with a linear FIR filter (Hammerstein structure) or migrate to memory polynomial DPD

For 5G NR signals with 100 MHz bandwidth at sub-6 GHz, pure LUT-based predistortion typically achieves only 5-10 dB ACLR improvement versus 15-20 dB for memory-capable models.

A predistorter whose output depends only on the instantaneous input sample, not on past values. LUT indexing is the primary implementation method for this class. The complex gain correction factor is a function of the instantaneous envelope magnitude: F(|x(n)|). This contrasts with models incorporating memory depth, which require tapped delay lines. Memoryless predistortion is effective for PAs where thermal and electrical memory effects are negligible, such as certain Class A amplifiers operating well below compression.

A table storing complex-valued correction factors indexed by quantized input magnitude. Each entry contains an in-phase (I) and quadrature (Q) component that multiplies the input signal to pre-compensate for PA nonlinearity. The table implements the function G(|x|) = A(|x|) * e^(j*Φ(|x|)), where A is amplitude correction and Φ is phase correction. Typical table sizes range from 64 to 1024 entries, balancing correction resolution against memory footprint in FPGA block RAM.

The process of mapping a continuous input envelope value to a discrete table index. The input magnitude range is divided into uniform or non-uniform intervals. Uniform quantization uses equal step sizes: index = floor(|x| / Δ). Non-uniform quantization allocates more entries to regions of rapid gain variation (near compression) and fewer to linear regions. Quantization error introduces residual nonlinearity, making optimal bin allocation critical for meeting stringent ACPR requirements.

Methods to reduce quantization error by estimating correction factors between table entries:

• Nearest-neighbor: Simplest, uses closest entry; introduces stair-step distortion
• Linear interpolation: Computes weighted average of two adjacent entries; smooths response
• Cubic interpolation: Uses four surrounding points for higher accuracy at increased computational cost
• Complex gain interpolation: Interpolates I and Q components separately, preserving phase continuity Interpolation enables smaller tables to achieve equivalent linearization performance.

Mechanisms for dynamically updating table entries to track time-varying PA characteristics due to temperature drift, aging, or channel frequency changes. Common strategies include:

• Linear interpolation update: Adjusts two adjacent entries proportionally based on the index error
• Secant method: Iteratively refines individual entries using gradient information
• Least mean squares (LMS) per-bin: Applies LMS adaptation independently to each active bin
• Bulk table reload: Periodically recomputes the entire LUT from an extracted model Adaptation convergence speed must exceed the rate of PA characteristic change.

Advanced LUT structures for multi-band or MIMO transmitters where multiple signals require simultaneous predistortion:

• Dual-port LUT: Single table with two read ports for concurrent dual-band correction
• Banked LUT: Multiple independent tables, each dedicated to a transmit chain or frequency band
• 3D LUT: Indexed by magnitude and an additional dimension such as frequency offset or envelope derivative
• Hierarchical LUT: Coarse table for rapid lookup with fine-resolution secondary table for critical regions These architectures exploit FPGA dual-port BRAM capabilities for efficient implementation.