LUT Partitioning

Partitioning breaks a high-dimensional LUT into a sum of lower-dimensional sub-tables. For example, a 2D LUT with memory depth addressing both instantaneous power and a delayed sample can be decomposed into two 1D LUTs. This exploits the fact that nonlinearity and memory effects are often separable, reducing storage from O(N²) to O(2N) while maintaining correction fidelity.

The primary benefit is exponential memory savings. A uniform 2D LUT with 256×256 entries requires 65,536 stored coefficients. Partitioning into two 256-entry 1D sub-tables reduces this to 512 coefficients—a 128:1 compression ratio. For 3D tables addressing multi-band scenarios, the savings are even more dramatic, making FPGA and ASIC implementations feasible within constrained block RAM budgets.

Partitioning introduces additional address computation logic to route input samples to the correct sub-table. Each sub-table requires its own indexing circuit based on the decomposed dimension. The trade-off is silicon area for memory: the combined addressing logic and smaller LUTs typically consume less total FPGA fabric than a single large LUT with simpler addressing, especially when using distributed RAM for sub-tables.

A key challenge is handling cross-terms—nonlinear interactions between different signal dimensions that pure decomposition would ignore. Advanced partitioning schemes add small cross-term LUTs to capture dominant inter-dimensional distortion products. For instance, a Hammerstein-Wiener partition uses a nonlinear static sub-table followed by a linear dynamic sub-table, with an optional cross-term table for residual correction.

Partitioned sub-tables can be adapted independently using separate LMS or RLS update loops. This enables parallel coefficient estimation, where each sub-table's error gradient is computed from its specific input dimension. Independent adaptation accelerates convergence because each sub-table has fewer parameters to optimize, and updates do not interfere across decomposed dimensions when the partitioning basis is orthogonal.

Partitioning alters interpolation requirements. A single large LUT may need bilinear or trilinear interpolation across multiple dimensions, which is computationally expensive. Decomposed sub-tables typically require only 1D linear interpolation per sub-table, significantly reducing multiplier usage. The combined interpolated outputs are then summed, trading a small increase in addition operations for a large reduction in multiplication complexity.

The spacing between adjacent entries in a look-up table, determining the resolution of the predistortion function. Partitioning directly trades granularity for memory savings.

• Uniform spacing: Equal step size across the input range, simple to implement
• Non-uniform spacing: Higher density in regions of rapid gain compression
• Trade-off: Finer granularity improves linearization but increases memory requirements exponentially with dimensionality

A mathematical technique for estimating predistortion values between discrete table entries to reduce quantization error. Partitioned LUTs often require interpolation across sub-table boundaries.

• Linear interpolation: Simple, low-complexity estimation between two adjacent entries
• Polynomial interpolation: Higher-order curve fitting for smoother transitions
• Boundary handling: Interpolation across partition edges requires careful coefficient alignment to prevent spectral regrowth

Techniques for reducing the total number of stored coefficients to minimize memory footprint and power consumption. Partitioning is a form of structural compression.

• Dimensionality reduction: Decomposing a multi-dimensional table into parallel lower-dimensional sub-tables
• Sparse representation: Storing only non-zero or significant coefficients
• Vector quantization: Clustering similar coefficient values to share entries across index ranges

The number of sequential historical signal samples used with the instantaneous index to address a multi-dimensional predistortion LUT. Memory depth dramatically increases table size.

• 1-tap (memoryless): Single-dimensional table indexed by instantaneous envelope only
• N-tap memory: N-dimensional table requiring N index calculations per sample
• Partitioning benefit: Decomposing an N-tap table into N parallel 1-tap sub-tables reduces storage from O(K^N) to O(N*K), where K is the number of entries per dimension

The hardware logic that calculates the memory address for a table entry based on quantized input signal magnitude and optional memory tap indices. Partitioned architectures require distributed addressing logic.

• Magnitude calculation: Computing instantaneous envelope (I^2 + Q^2 or sqrt approximation)
• Quantization mapping: Converting continuous magnitude to discrete address space
• Multi-table routing: Directing each memory tap to its corresponding sub-table in a partitioned architecture

The state where iterative adaptation algorithms have minimized the error signal to a stable residual level. Partitioned LUTs may exhibit different convergence rates across sub-tables.

• Independent convergence: Each sub-table adapts at its own rate based on local signal statistics
• Cross-coupling effects: Adaptation in one partition can perturb the error surface of adjacent partitions
• Staggered updates: Updating partitions sequentially rather than simultaneously can improve overall loop stability