Inferensys

Glossary

LUT Indexing

LUT indexing is the process of mapping an input signal's instantaneous power or magnitude to a specific memory address within a predistortion look-up table to retrieve the corresponding correction coefficient.
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ADDRESS GENERATION

What is LUT Indexing?

The fundamental mechanism that maps an input signal's instantaneous power or magnitude to a specific memory address within a predistortion look-up table.

LUT Indexing is the process of mapping an input signal's instantaneous power or magnitude to a specific memory address within the predistortion look-up table. The indexing function computes a quantized address from the signal envelope, enabling real-time retrieval of the corresponding complex-gain correction coefficient to linearize the power amplifier.

The indexing scheme directly determines LUT Granularity and correction accuracy. Uniform indexing divides the dynamic range into equally spaced bins, while Non-Uniform LUT strategies allocate higher address density in regions of rapid gain compression. Multi-dimensional indexing incorporates LUT Memory Depth by concatenating the instantaneous magnitude with delayed signal taps to address memory effects.

ADDRESS GENERATION MECHANISMS

Key Characteristics of LUT Indexing

The process of mapping an input signal's instantaneous power or magnitude to a specific memory address within the predistortion look-up table. Effective indexing is critical for minimizing quantization error and ensuring the correct predistortion coefficient is applied in real time.

01

Magnitude-Based Addressing

The most fundamental indexing method where the instantaneous envelope magnitude |x(n)| of the complex baseband input signal is computed and quantized to form the memory address. This scalar index maps directly to a single-entry complex-gain correction factor. The address calculation is typically Address = floor(|x(n)| / Step_Size), creating a one-dimensional table that corrects static AM-AM and AM-PM distortion but ignores memory effects.

02

Power-Based Indexing

Uses the instantaneous input power |x(n)|² rather than magnitude to generate the table address. This provides a non-uniform spacing in terms of magnitude, naturally allocating higher resolution in the compression region where the amplifier's gain curve changes most rapidly. Power indexing is computationally efficient as it avoids a square-root operation and better matches the physical origin of nonlinearity in semiconductor junctions.

03

Multi-Dimensional Memory Indexing

Extends the address space to include delayed signal samples to compensate for memory effects. A 2D LUT uses the current magnitude |x(n)| and a previous magnitude |x(n-1)| as row and column indices. This creates an N×N matrix of coefficients that captures first-order memory. Higher-dimensional indexing with additional taps increases correction fidelity but causes exponential growth in memory requirements, often mitigated by LUT partitioning or sparse interpolation.

04

Uniform vs. Non-Uniform Quantization

Uniform indexing divides the input dynamic range into equal-amplitude steps, simplifying hardware addressing but wasting resolution in linear regions. Non-uniform indexing uses variable step sizes—typically derived from a companding function like μ-law or a signal-dependent PDF—to concentrate entries where the amplifier's gain derivative is steepest. This optimizes correction accuracy for a fixed table size and is essential for signals with high peak-to-average power ratios.

05

Address Overflow and Underflow Protection

Hardware indexing logic must handle signals exceeding the LUT's designed dynamic range. Saturation logic clamps the address to the maximum valid index when the input envelope exceeds the table's upper bound, preventing memory access violations. Underflow near zero magnitude is typically handled by forcing the lowest address. Proper normalization of the input signal to match the table's span is critical to avoid clipping-induced spectral regrowth.

06

Interpolation-Aware Indexing

When LUT interpolation is employed, the indexing logic must output not only the base address but also the fractional offset between adjacent entries. For linear interpolation, the indexer computes Address_Base = floor(Normalized_Input) and Fraction = Normalized_Input - Address_Base. The predistorter then reads coefficients at Address_Base and Address_Base+1, blending them using the fraction. This dramatically reduces quantization error without increasing table size.

LUT INDEXING ESSENTIALS

Frequently Asked Questions

Clear answers to the most common questions about mapping input signal characteristics to predistortion table addresses in real-time systems.

LUT indexing is the process of mapping an input signal's instantaneous power or magnitude to a specific memory address within the predistortion look-up table. The system first computes the envelope of the incoming complex baseband signal, typically using the formula |x(n)| = sqrt(I² + Q²). This magnitude value is then quantized into a discrete integer that serves as the physical memory address. For example, a 10-bit quantizer maps the continuous envelope into one of 1024 distinct table entries. The indexed address retrieves a pre-computed complex gain coefficient that is multiplied with the original signal to counteract the power amplifier's nonlinearity. This direct mapping ensures deterministic, single-cycle access latency in hardware implementations.

REAL-TIME LINEARIZATION COMPARISON

LUT Indexing vs. Polynomial Evaluation

Comparison of computational complexity, memory requirements, and linearization performance between look-up table indexing and direct polynomial evaluation for digital predistortion.

FeatureLUT IndexingPolynomial EvaluationHybrid LUT-Polynomial

Computational Complexity

O(1) lookup + interpolation

O(N) multiply-accumulate

O(1) lookup + reduced polynomial

Memory Footprint

High (2^B × 32-bit entries)

Low (coefficients only)

Moderate (reduced table + coefficients)

Latency per Sample

1-3 clock cycles

10-50 clock cycles

3-8 clock cycles

Adaptation Speed

Per-entry update (fast local)

Full coefficient recomputation (slow)

Table update + coefficient refresh

Quantization Error Sensitivity

Moderate (address quantization)

None (continuous function)

Low (interpolation smooths transitions)

Hardware Multiplier Requirement

Suitability for Strong Memory Effects

Requires multi-dimensional LUT

Native support via memory polynomial

Good compromise

Typical ACLR Improvement

-45 to -55 dBc

-50 to -60 dBc

-48 to -58 dBc

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.