LUT Addressing

The fundamental addressing scheme where the instantaneous envelope magnitude |x(n)| of the complex baseband input signal is quantized to form the primary memory address. An envelope detector computes sqrt(I² + Q²) or approximates it using the CORDIC algorithm. The resulting magnitude is scaled and truncated to match the LUT's address bus width. This one-dimensional addressing assumes the power amplifier's nonlinearity is primarily a function of instantaneous input power, making it suitable for memoryless or weakly nonlinear PAs. The address calculation must complete within a single sample clock cycle to maintain real-time throughput.

For power amplifiers exhibiting significant memory effects, the LUT address becomes a vector incorporating both the current sample and delayed samples. A typical 2D addressing scheme uses the current magnitude |x(n)| and a delayed magnitude |x(n-1)| to form a 2D address space. The total address is computed as:

• Address = Index[x(n)] + N * Index[x(n-1)] where N is the number of quantization levels per dimension. This captures the PA's dependence on prior signal states. Higher-dimensional addressing (3D or more) increases correction accuracy but causes exponential growth in memory requirements, often necessitating sparse table or multiplexed addressing techniques.

The continuous input magnitude must be mapped to a finite set of discrete addresses. An N-bit quantizer divides the input dynamic range into 2^N uniformly spaced regions. Key design considerations include:

• Overflow protection: Inputs exceeding the maximum expected magnitude must saturate at the highest address rather than wrapping around.
• Underflow handling: Signals below the minimum threshold map to address 0, typically corresponding to linear gain.
• Non-uniform quantization: Allocating more bits to the compression region (high power) and fewer to the linear region optimizes correction accuracy for a given address width. The quantization step size directly impacts residual distortion floor.

In high-speed FPGA or ASIC implementations, address generation is implemented as a hardware pipeline to meet timing closure. The pipeline stages typically include:

1. Magnitude computation: I² + Q² using dedicated DSP slices, followed by square root approximation.
2. Scaling and normalization: Multiplying by a programmable gain factor to map the signal range to the LUT address space.
3. Delay line management: Storing historical magnitudes in a shift register for multi-dimensional addressing.
4. Address assembly: Concatenating or summing individual dimension indices into the final physical memory address. Pipeline registers are inserted between stages to maintain high clock frequencies exceeding 300 MHz in modern implementations.

To optimize correction accuracy within limited memory budgets, non-uniform addressing schemes concentrate table entries where the PA nonlinearity changes most rapidly. Common approaches include:

• μ-law or A-law companding: Applying logarithmic compression to the magnitude before quantization, allocating more addresses to low and medium power regions.
• Segmented addressing: Dividing the input range into multiple segments with different quantization step sizes, using a segment decoder to select the appropriate sub-table.
• Adaptive spacing: Dynamically adjusting address boundaries based on the PA's measured AM-AM and AM-PM characteristics. These techniques can reduce memory requirements by 50–75% compared to uniform addressing while maintaining equivalent linearization performance.

In adaptive DPD systems, the LUT coefficients must be updated while the predistorter continues operating without interruption. The ping-pong addressing architecture uses two identical memory banks:

• Active bank: Connected to the predistortion datapath, performing real-time correction.
• Shadow bank: Receiving coefficient updates from the adaptation processor. A single-bit control signal swaps the roles of the two banks after the shadow bank update is complete. The address generation logic must drive both banks simultaneously, with a multiplexer selecting the active output. This ensures glitch-free transitions and prevents spectral transients during coefficient updates.