Direct LUT Architecture

The predistorter operates in a feed-forward open-loop configuration, placed directly between the baseband modulator and the power amplifier. The input complex baseband signal's instantaneous magnitude is computed, quantized, and used to address the LUT. The retrieved complex-gain coefficient is immediately multiplied with the input sample. This architecture introduces minimal processing latency—typically a single clock cycle for the table lookup and one complex multiplication—making it ideal for wideband signals where group delay must be strictly controlled.

Each LUT entry stores a single complex-valued correction factor that simultaneously compensates for both AM-AM and AM-PM distortion. The stored value represents the inverse of the power amplifier's complex gain at that specific input magnitude:

• Magnitude component: Expands gain to counteract PA compression
• Phase component: Rotates the signal to cancel AM-PM conversion This unified complex correction eliminates the need for separate amplitude and phase LUTs, reducing memory requirements by approximately 50% compared to dual-table architectures.

The LUT address is derived from the instantaneous envelope magnitude of the input signal, computed as √(I² + Q²). This magnitude is quantized to match the table's address space. Key indexing considerations:

• Uniform quantization: Equal spacing across the magnitude range, simplest to implement
• Non-uniform quantization: Higher density in compression regions for improved accuracy
• Address calculation: Typically uses the upper bits of the magnitude word after magnitude computation
• Overflow protection: Magnitude values exceeding the maximum index are saturated to the last table entry

A fundamental limitation of the basic Direct LUT Architecture is that it is memoryless by design—each correction depends solely on the current input sample. For power amplifiers exhibiting significant memory effects, this single-dimensional mapping cannot capture the history-dependent nonlinear behavior. Extensions to address this include:

• Multi-dimensional LUTs: Indexing based on current magnitude plus delayed magnitude values
• Hammerstein cascades: LUT followed by a linear filter to model memory
• Memory polynomial augmentation: Combining the direct LUT with FIR filter taps Without these extensions, residual memory-effect distortion limits ACLR improvement.

The Direct LUT Architecture maps efficiently to FPGA and ASIC implementations due to its regular structure:

• Block RAM utilization: LUT coefficients stored in dedicated BRAM blocks with single-cycle read access
• DSP slice requirements: One complex multiplier (3-4 DSP48 slices) for gain application
• Magnitude computation: CORDIC or piecewise-linear approximation for √(I² + Q²)
• Typical resource budget: A 256-entry complex-gain LUT with interpolation consumes approximately 2 BRAMs and 5 DSP slices
• Throughput: Sustains one sample per clock at 300+ MHz on modern FPGAs

Although the signal path is feed-forward, the coefficient adaptation operates through a separate training loop. The Direct LUT Architecture is typically paired with an Indirect Learning Architecture for coefficient updates:

• The PA output is sampled through a feedback receiver
• The post-distorter (inverse model) is trained to minimize error
• Coefficients are periodically copied to the forward-path predistorter LUT This separation ensures that adaptation latency does not affect the real-time signal path, maintaining constant throughput during coefficient updates.

A predistortion table architecture that stores a single complex-valued coefficient per entry to simultaneously correct both amplitude (AM-AM) and phase (AM-PM) distortion. This is the fundamental storage element of the Direct LUT Architecture.

• Each entry is a complex number: I + jQ
• Applied as a complex multiplication to the input signal
• Eliminates the need for separate amplitude and phase correction tables

The process of mapping an input signal's instantaneous power or magnitude to a specific memory address within the predistortion look-up table. In Direct LUT Architecture, the index is derived directly from the envelope detector output.

• Common indexing: |x(n)|^2 (power) or |x(n)| (magnitude)
• Quantization of the continuous envelope into discrete address space
• Determines which correction coefficient is applied at each sample instant

A mathematical technique for estimating predistortion values between discrete table entries to reduce quantization error and improve linearization accuracy. Essential when table granularity is limited by memory constraints.

• Linear interpolation: Simplest, uses two adjacent entries
• Polynomial interpolation: Higher accuracy, more compute-intensive
• Reduces required table size for a given ACLR target
• Direct LUT architectures often combine sparse tables with real-time interpolation

The spacing between adjacent entries in a look-up table, determining the resolution of the predistortion function across the input signal dynamic range. A critical design parameter in Direct LUT Architecture.

• Finer granularity = better linearization, larger memory footprint
• Coarser granularity = smaller memory, higher interpolation error
• Typical implementations: 64 to 4096 entries
• Non-uniform LUT allocates higher density in regions of rapid gain compression

The distortion introduced by representing continuous predistortion functions with a finite number of discrete amplitude levels within the look-up table. This is the primary performance limiter in Direct LUT Architectures.

• Arises from finite bit-width of stored coefficients
• Manifests as spectral regrowth and elevated noise floor
• Trade-off: more bits = higher ACLR improvement, larger memory
• Typical coefficient precision: 12-16 bits for I and Q components

A dual-buffer memory architecture where one look-up table is actively used for predistortion while the other is being updated in the background. Ensures seamless, glitch-free coefficient switching in adaptive Direct LUT systems.

• Eliminates transient distortion during table updates
• Requires double the memory of a single LUT
• Common in FPGA implementations with block RAM
• Switching triggered by adaptation cycle completion