I/Q Mismatch Filter

Unlike standard linear filters, an I/Q mismatch filter implements a widely-linear architecture. It processes both the standard signal x[n] and its complex conjugate x*[n] through separate filter taps. This is mathematically necessary because the I/Q imbalance creates an image signal that is a conjugate version of the desired signal. The filter output is y[n] = w1[n] * x[n] + w2[n] * x*[n], where w1 and w2 are the direct and image filter coefficients.

A simple scalar correction cannot fix frequency-dependent I/Q imbalance caused by mismatched analog low-pass filters or PCB trace length differences. The I/Q mismatch filter uses multiple taps to model the gain ripple and phase ripple across the signal bandwidth. Each tap compensates for a specific delay, effectively flattening the frequency response of the I and Q paths to restore orthogonality at all frequencies within the band of interest.

The coefficients of the image filter w2[n] are directly related to the I/Q mismatch coefficient at each frequency. For a purely frequency-independent imbalance, the filter reduces to a single complex tap. For frequency-dependent cases, the coefficients exhibit a specific symmetry: the image filter's frequency response is a scaled, mirrored version of the direct path's error. This property is exploited in blind estimation algorithms to reduce the number of unknown parameters.

Analog impairments drift with temperature, voltage, and aging. An I/Q mismatch filter often operates in a closed-loop adaptive configuration using algorithms like Least Mean Squares (LMS). The filter continuously correlates the output signal with its own conjugate to detect residual image leakage. The error signal drives coefficient updates, ensuring the Image Rejection Ratio (IRR) remains maximized during live operation without interrupting the transmission.

In a direct-conversion transmitter, the I/Q mismatch filter sits immediately before the Digital Pre-Distortion (DPD) block in the signal chain. This ordering is critical: the DPD expects a perfectly orthogonal I/Q input to accurately model the power amplifier's nonlinearity. If I/Q imbalance is not corrected first, the DPD will attempt to linearize the distorted image signal, leading to model instability and degraded Adjacent Channel Leakage Ratio (ACLR).

For real-time wideband signals, the I/Q mismatch filter is implemented in FPGA logic using a systolic array of complex multipliers. A typical 5G NR 100 MHz correction filter might use 5-11 taps per conjugate branch. The architecture is optimized to exploit the symmetry of the coefficients, often folding the design to reuse DSP48 slices. Latency through the filter must be deterministic and matched with the observation receiver path to prevent loop instability.