Predistorter Core

The core is implemented as a continuous dataflow pipeline where processing is triggered by the arrival of new baseband samples rather than a centralized program counter. This maps directly to the streaming nature of the forward-path signal.

• AXI4-Stream interfaces provide back-pressure capable, unidirectional connections to preceding CFR blocks and subsequent DAC interfaces
• No frame buffering is required; samples are processed sample-by-sample with deterministic latency
• The architecture naturally supports sample rate conversion (SRC) interfaces when the predistorter operates at a different rate than the DAC

The predistorter core exclusively uses fixed-point numerical representation to minimize FPGA resource consumption and maximize clock speed. Floating-point units are avoided entirely in the forward path.

• Complex multipliers are constructed from DSP48 slices configured for high-speed multiply-accumulate operations
• Coefficient quantization trades off bit-width against linearization accuracy—typically 16 to 18 bits for I/Q paths
• Saturation and rounding modes are explicitly defined to prevent overflow and limit cycles during sustained operation

To meet the multi-hundred-megahertz clock frequencies required for wideband signals, the core's combinational logic is aggressively pipelined. Register stages are inserted between every major arithmetic operation.

• Pipelining increases maximum clock frequency at the cost of added latency—a trade-off that is carefully managed to stay within the system's latency budget
• The complex multiplier and polynomial evaluation stages are the most heavily pipelined blocks
• Retiming optimizations during synthesis automatically balance register placement for timing closure

The core's computational heart is a hardware-optimized memory polynomial evaluator that computes the predistorted output as a function of the current and delayed input samples.

• The polynomial structure captures both static nonlinearity (AM-AM, AM-PM) and memory effects (thermal, electrical) of the power amplifier
• Look-up table (LUT) DPD variants replace polynomial computation with indexed complex gain values for lower complexity
• The number of Volterra kernel terms implemented directly determines DSP48 slice utilization and linearization bandwidth capability

The predistorter core typically operates in a dedicated clock domain, requiring robust clock domain crossing (CDC) logic at its boundaries. This isolates the processing pipeline from the asynchronous timing of data converter interfaces.

• Asynchronous FIFOs with Gray-coded pointers safely transfer samples between the core's clock domain and the JESD204B or RFSoC DAC domain
• Metastability hardening through multi-stage synchronizer chains is mandatory on all control and data signals crossing domains
• CDC constraints are rigorously specified in Xilinx Vivado to ensure static timing analysis validates all crossings

The predistorter core supports real-time adaptation through a double-buffered coefficient memory. New predistortion parameters are loaded into a shadow register set and atomically swapped into the active path.

• This enables indirect learning architecture (ILA) or direct learning architecture (DLA) updates without interrupting transmission
• The coefficient update interface is typically an AXI4-Lite slave port driven by an embedded processor (e.g., Zynq UltraScale+ ARM core)
• Atomic swapping prevents the predistorter from ever applying a partially updated, inconsistent set of coefficients

A dedicated high-speed arithmetic block in Xilinx FPGAs that performs the multiply-accumulate (MAC) operations fundamental to polynomial evaluation. A single DSP48 can compute a 25x18-bit multiply and 48-bit accumulate in one clock cycle.

• Implements complex multipliers for gain correction
• Cascades without fabric routing for high-speed filter chains
• Critical resource for meeting < 100 ns latency budgets

A numerical representation where the radix point has a fixed position, trading dynamic range for hardware efficiency. Predistorter cores use fixed-point to avoid the high latency and resource cost of floating-point units.

• Typical formats: Q16.14 for coefficients, Q14.14 for signals
• Requires careful overflow and rounding analysis
• Directly impacts Error Vector Magnitude (EVM) performance

A hardware optimization that inserts register stages between combinational logic clouds to increase the maximum clock frequency. In a predistorter core, pipelining breaks the long critical path through polynomial evaluation and complex multiplication.

• Enables operation at 491.52 MHz for 5G NR bandwidths
• Adds latency measured in clock cycles, not microseconds
• Essential for meeting timing closure in 16nm FinFET nodes

The process of converting high-precision floating-point DPD coefficients into fixed-point representations with a finite bit width. Quantization introduces correction error that must be balanced against hardware savings.

• 16-bit coefficients typically achieve < -50 dB EVM
• Aggressive 12-bit quantization saves 40% DSP resources
• Validated through bit-accurate simulation before synthesis