Hardware-in-the-Loop (HIL)

The core of HIL for DPD is a high-fidelity, real-time simulation of the power amplifier and feedback path. This emulator, often running on a separate FPGA or a high-speed processor, executes a behavioral model—such as a Memory Polynomial or Generalized Memory Polynomial—to generate a distorted output sample for every input sample. The emulation must run with deterministic latency, typically matching the sample rate of the physical DPD core, to close the loop without timing violations. This allows the DPD's adaptive algorithm to converge as if it were connected to a real amplifier, revealing issues in coefficient quantization or fixed-point arithmetic precision that pure software simulations miss.

HIL testing validates the physical-layer interfaces of the DPD prototype. The testbench emulates the exact timing and protocol of JESD204B or AXI4-Stream interfaces, including lane alignment, deterministic latency, and SERDES initialization sequences. A critical aspect tested here is Clock Domain Crossing (CDC)—the DPD processing logic, data converter interfaces, and the emulated PA model often run on asynchronous clocks. HIL exposes metastability issues, FIFO overflows, and timing violations that are invisible in cycle-accurate RTL simulation, ensuring the predistorter core can be reliably integrated with physical DACs and ADCs.

The primary value of HIL is validating the Indirect Learning Architecture (ILA) or Direct Learning Architecture (DLA) in a dynamic, closed-loop scenario. The physical DPD core transmits a predistorted signal into the emulated PA model. The emulator generates a distorted output, which is fed back to the DPD's coefficient estimation engine. The HIL system can inject controlled perturbations—such as a sudden change in the emulated PA's gain compression curve or a temperature-induced drift in thermal memory effects—to verify that the real-time adaptation algorithm re-converges without instability or signal interruption. This validates the entire adaptive control loop before connecting to expensive RF hardware.

HIL setups are instrumented to measure the exact end-to-end latency of the DPD processing chain, from input sample to predistorted output. The testbench can stress the pipelining architecture by varying the emulated feedback delay, simulating different cable lengths or filter group delays in the observation path. This validates that the time alignment algorithm in the DPD's feedback path can correctly synchronize the reference and observed signals under worst-case latency conditions. Throughput is verified by running the system at the target sample rate for extended periods, checking for sample drops or backpressure events on the AXI4-Stream interfaces.

HIL testing provides a controlled environment for precise performance measurement. The emulated PA output is captured and analyzed to calculate key figures of merit: Error Vector Magnitude (EVM) for in-band distortion, Adjacent Channel Leakage Ratio (ACLR) for spectral regrowth, and Normalized Mean Squared Error (NMSE) for model accuracy. Because the reference signal and the emulated PA model are perfectly known, the HIL system can decompose the residual error to isolate contributions from coefficient quantization noise, fixed-point arithmetic rounding, or algorithmic limitations. This diagnostic capability is impossible with a physical PA, where measurement noise obscures these fine-grained error sources.

Modern HIL testbenches for DPD often leverage heterogeneous platforms like the Xilinx RFSoC or Zynq UltraScale+. The physical DPD core is synthesized into the FPGA fabric, while the PA behavioral model and the adaptive control software run on the integrated ARM processing cores. This architecture allows engineers to validate the hardware-software partitioning—for example, testing whether the DSP48 slices handle the high-speed predistortion while the ARM cores manage slower coefficient estimation updates. The HIL setup verifies the AXI bus bandwidth and latency between the processing system and the programmable logic, ensuring the dataflow architecture meets real-time constraints.

The capability of a DPD system to update its predistortion function continuously during live transmission without interrupting the signal. In HIL testing, real-time adaptation is validated by simulating dynamic thermal and frequency-hopping scenarios that stress the closed-loop update rate.

• Validates coefficient convergence under transient conditions
• Tests tracking of thermal memory effects and gain compression drift
• Ensures the predistorter core maintains linearity without glitching

A critical signal processing step that precisely synchronizes the transmitted reference signal with the received feedback signal. In HIL environments, time alignment must be verified with sub-sample accuracy to prevent model extraction errors that would mask true hardware latency.

• Compensates for feedback path group delay
• Uses cross-correlation techniques for fractional sample alignment
• Errors here propagate directly into coefficient estimation algorithms

The observation receiver chain that couples, downconverts, and digitizes a sample of the power amplifier's output. HIL testing allows this feedback path to be validated against a simulated PA model before committing to RF hardware, catching issues in sample rate conversion and JESD204B interface timing.

• Includes coupler, mixer, anti-alias filter, and ADC
• Must preserve error vector magnitude (EVM) fidelity
• HIL simulates path impairments like IQ imbalance

The process of converting high-precision DPD model parameters into a fixed-point arithmetic representation with a finite number of bits. HIL testing quantifies the linearization degradation caused by quantization, enabling hardware engineers to optimize DSP48 slice utilization against ACLR performance.

• Trade-off between bit-width and look-up table (LUT) DPD accuracy
• Validates that quantized coefficients don't cause spectral regrowth
• Critical for memory polynomial implementations on FPGAs

The passage of a signal between two asynchronous clock domains on an FPGA. HIL testing exposes CDC issues that only manifest when the predistorter core logic runs at a different rate than the SERDES-driven data converter interfaces, revealing metastability bugs before silicon integration.

• Requires proper synchronization and handshaking
• Common between processing logic and JESD204B lanes
• HIL simulates realistic clock jitter and drift scenarios

The nonlinear region of a power amplifier's operation where an increase in input power no longer produces a proportional increase in output power. HIL testing drives the predistorter core with signals that push the simulated PA deep into compression, validating that the indirect learning architecture (ILA) can linearize even severe nonlinearities.

• Primary distortion mechanism targeted by DPD
• Characterized by AM-AM and AM-PM conversion curves
• HIL enables safe testing at destructive power levels