Fixed-Point Arithmetic

In a fixed-point format, the number of integer and fractional bits is static and defined at design time. This provides a strict, known trade-off between dynamic range and precision. Unlike floating-point, which offers a wide dynamic range at the cost of variable precision, fixed-point guarantees constant absolute precision across its entire representable range. For DPD, this means the quantization error for small and large signal samples is predictable, simplifying error vector magnitude (EVM) budgeting.

A fixed-point number is stored and operated on as a standard two's complement integer. The hardware—such as an FPGA's DSP48 slice—performs pure integer multiplication and addition. The fixed-point interpretation is a design abstraction. This allows a single DSP slice to compute a fixed-point multiply-accumulate operation in one clock cycle, achieving the maximum possible throughput without the multi-cycle latency and resource overhead of a floating-point unit.

The position of the implicit radix point is conventionally described using Q-format notation. The notation Qm.n specifies a number with m integer bits (including the sign bit) and n fractional bits. For example:

• Q1.15: A 16-bit word with 1 sign/integer bit and 15 fractional bits, representing values from -1.0 to approximately 0.99997.
• Q5.11: A 16-bit word with 5 integer bits and 11 fractional bits, providing a wider dynamic range but coarser resolution. Selecting the correct Q-format for each stage of a DPD datapath is critical to prevent overflow while minimizing quantization noise.

When a mathematical operation produces a result that requires more bits than the destination format, the value must be quantized. This involves truncation or rounding, introducing quantization error. In a DPD system, coefficient quantization directly impacts linearization performance. Common rounding modes include:

• Truncation: Simply discarding least-significant bits, which introduces a negative bias.
• Convergent Rounding: Rounding to the nearest representable value, with ties going to the nearest even number to eliminate statistical bias. The choice of rounding mode affects the noise floor and potential spectral regrowth in the corrected signal.

Implementing a complex multiplier in fixed-point logic consumes a fraction of the FPGA resources required by an IEEE 754 single-precision floating-point equivalent. A single-precision floating-point multiplier can require multiple DSP48 slices and hundreds of logic cells, while a fixed-point complex multiplier can be mapped to as few as 3 DSP48 slices. For a high-sample-rate DPD core with multiple parallel paths, this resource savings is the difference between fitting a design on a device and requiring a larger, more expensive FPGA.

A fixed-point operation can produce a result that exceeds the representable range of the destination format, causing overflow. In two's complement arithmetic, a severe overflow wraps around from the maximum positive value to the minimum negative value, creating a catastrophic discontinuity in the DPD signal. To prevent this, hardware designs employ saturation logic that clips the output to the maximum or minimum representable value upon overflow, providing a graceful, non-linear limiting behavior that is far less destructive to the transmitted spectrum.

The process of converting high-precision DPD model parameters into a fixed-point representation with a finite number of bits. This involves a direct trade-off: wider bit widths preserve linearization accuracy but consume more DSP slices and block RAM, while narrower widths save resources but introduce quantization noise that degrades Error Vector Magnitude (EVM). Optimal quantization requires analyzing the dynamic range of each coefficient and allocating integer and fractional bits accordingly.

A dedicated high-speed arithmetic logic block within Xilinx FPGAs optimized for the multiply-accumulate (MAC) operations fundamental to fixed-point DPD. Each slice contains a 25x18-bit multiplier, an accumulator, and an adder, enabling efficient implementation of complex multipliers and FIR filter taps. Fixed-point DPD architectures map polynomial terms directly onto cascaded DSP48 chains to maximize throughput while minimizing fabric resource usage.

A hardware arithmetic unit that computes the product of two complex numbers, a fundamental building block in fixed-point DPD for applying complex-valued gain corrections to in-phase (I) and quadrature (Q) signal components. In fixed-point implementation, a single complex multiplication requires four real multiplications and two additions. Careful fractional bit alignment after each multiplication prevents overflow and maintains precision through the datapath.

A hardware optimization technique that inserts register stages between combinational logic operations to increase the maximum clock frequency. In fixed-point DPD cores, pipelining is essential for meeting tight latency budgets. Key considerations include:

• Latency vs. throughput: More stages increase clock speed but add delay
• Bit-width growth: Each pipeline register must accommodate the full precision of intermediate results
• Feedback path alignment: Pipeline delays in the forward path must be matched in the observation path for accurate model extraction

The passage of a signal between two asynchronous clock domains on an FPGA, a critical design challenge in fixed-point DPD systems where the processing logic and data converter interfaces operate at different rates. Fixed-point data crossing clock domains requires careful synchronization using dual-clock FIFOs or handshake protocols to prevent metastability. The bit width of the crossing path must preserve the full fixed-point precision to avoid injecting quantization errors into the predistortion signal.

A hardware design paradigm where processing is triggered by the availability of input data rather than a centralized program counter. This naturally maps the streaming nature of fixed-point DPD signal processing, where samples flow continuously through multipliers, adders, and look-up tables. In a dataflow design, each processing stage operates independently, with fixed-point word lengths optimized per stage to balance resource usage against the signal-to-quantization-noise ratio (SQNR).