Direct Learning Architecture (DLA)

Unlike Indirect Learning Architecture (ILA), DLA directly identifies the predistorter function by modeling the inverse nonlinearity of the power amplifier. The algorithm minimizes the error between the desired transmitted signal and the actual PA output, solving for the predistorter coefficients that produce the optimal pre-distorted input. This approach explicitly accounts for the cascade of predistorter and PA as a single system.

DLA operates in a closed-loop configuration where the predistorter output feeds the PA, and the PA output is observed through a feedback path. The estimation algorithm iteratively adjusts coefficients to minimize the error vector magnitude (EVM) between the reference signal and the attenuated PA output. This continuous feedback ensures the system tracks changes in PA nonlinearity due to temperature drift, aging, or frequency hopping.

DLA does not require a separate PA behavioral model to be extracted before computing the predistorter. The architecture directly estimates the predistorter parameters from input-output measurements, making it robust to model mismatch errors. This is particularly advantageous when the PA exhibits complex nonlinearities that are difficult to capture with standard models like memory polynomials or Volterra series.

Because the PA sits inside the estimation loop, the relationship between the predistorter coefficients and the observed error is inherently nonlinear. DLA requires iterative nonlinear optimization algorithms such as Levenberg-Marquardt, Gauss-Newton, or stochastic gradient descent to converge to the optimal coefficients. This computational complexity is a key trade-off compared to the linear-in-parameters estimation of ILA.

Accurate time alignment between the reference signal and the feedback observation is critical in DLA. Even sub-sample misalignments introduce phase errors that degrade coefficient estimation and linearization performance. DLA implementations typically incorporate cross-correlation-based alignment or fractional delay filters to achieve picosecond-level synchronization between the forward and observation paths.

On FPGA or ASIC platforms, DLA's iterative optimization is often partitioned between hardware and software. The predistorter core operates in real-time on the FPGA fabric using fixed-point arithmetic, while coefficient estimation runs on an embedded processor (e.g., ARM Cortex in a Zynq UltraScale+) or a soft-core microcontroller. High-Level Synthesis (HLS) tools accelerate the development of custom DLA estimation pipelines.

The primary alternative to DLA. In ILA, a post-distorter is identified by placing it after the PA in the training path. The converged post-distorter coefficients are then copied directly to the predistorter in the forward path. This avoids the assumption of a known PA model during identification, but can be sensitive to measurement noise in the feedback loop.

The process of deriving a behavioral model from observed input-output data. In a DLA context, this involves estimating the inverse PA characteristic. Common methods include:

• Least Squares (LS): A batch algorithm minimizing the squared error between the desired and actual predistorter output.
• Recursive Least Squares (RLS): An adaptive algorithm that updates the inverse model iteratively, suitable for tracking time-varying PA behavior.
• LMS/Newton: Gradient-based methods for computationally efficient coefficient updates.

A critical preprocessing step for any DPD learning architecture. Before model extraction, the transmitted reference signal and the observed feedback signal must be precisely synchronized in time. A misalignment of even a fraction of a sample can cause the DLA to model the delay rather than the PA nonlinearity, severely degrading EVM and ACLR performance. Techniques include cross-correlation and fractional delay filters.

The process of converting high-precision floating-point DPD coefficients, derived by the DLA algorithm, into a fixed-point representation for hardware implementation. This involves a critical trade-off:

• Word Length: More bits preserve linearization accuracy but consume more DSP48 slices and logic.
• Truncation Error: Quantization noise can introduce residual distortion, partially negating the DLA's correction.
• Optimization: The goal is to find the minimum bit width that meets the target EVM specification.

The capability of a DLA-based system to update its predistortion function continuously during live transmission. Unlike offline training, this closed-loop process tracks dynamic changes in the PA's nonlinearity caused by:

• Thermal Memory Effects: Transistor heating alters gain characteristics.
• Aging: Long-term component drift.
• Frequency Hopping: Switching channels changes the PA's impedance match. This ensures consistent linearization without interrupting the communication link.

The observation receiver chain that provides the distorted PA output signal to the DLA estimation block. Its quality directly limits DLA performance. Key components include:

• Coupler: Samples a fraction of the high-power RF output.
• Downconverter: Mixes the RF signal to an intermediate frequency or baseband.
• ADC: Digitizes the signal for processing. The ADC's SINAD and bandwidth must exceed the predistorted signal's requirements to avoid limiting the correction capability.