Clock Domain Crossing (CDC)

The fundamental physical phenomenon where a flip-flop enters an unstable, oscillating state when its input signal changes within the setup-and-hold timing window. In CDC paths, a signal from a source clock domain arrives asynchronously relative to the destination clock, creating a non-zero probability of violating these timing constraints. The flip-flop's output may hover at an intermediate voltage level for an unbounded resolution time before settling to a valid logic level, propagating indeterminate values into downstream logic. Mean Time Between Failures (MTBF) quantifies metastability risk and is exponentially improved by adding synchronizer stages.

The most common and fundamental CDC circuit, consisting of two or more sequentially connected flip-flops clocked by the destination domain. The first flip-flop samples the asynchronous input and may become metastable, but the second flip-flop provides a full clock period for the first stage to resolve before sampling its output. This architecture assumes the input signal is a single-bit, level-based control signal that changes infrequently relative to the destination clock. It does not guarantee safe transfer of multi-bit data buses or pulsed signals, which require specialized handshake or FIFO mechanisms.

Transferring parallel data buses across clock domains cannot be accomplished with independent two-flop synchronizers on each bit. Due to data skew, individual bits may be sampled in different destination clock cycles, corrupting the coherent value. Safe multi-bit CDC requires:

• Gray coding: Encoding where only one bit changes per state transition, suitable for counters and pointers.
• Handshake protocols: Request-acknowledge signaling that gates data capture.
• Asynchronous FIFOs: Dual-port memory structures with independent read/write clocks, using Gray-coded pointers for full/empty flag generation. In DPD systems, asynchronous FIFOs are the primary mechanism for crossing streaming I/Q sample data between processing and converter clock domains.

The workhorse of streaming CDC in DPD pipelines, an asynchronous FIFO uses a dual-port RAM buffer with independent read and write clock domains. Write and read pointers are maintained in each domain and cross to the opposite domain using Gray-coded synchronizers to generate full and empty status flags. The Gray encoding ensures that only one bit transitions per pointer increment, eliminating multi-bit sampling ambiguity. Key design parameters include FIFO depth (calculated from the maximum burst size and clock ratio) and almost-full/almost-empty thresholds for flow control. In FPGA-based DPD, asynchronous FIFOs decouple the predistorter core's processing clock from the JESD204B or RFSoC data converter sample clocks.

Standard Static Timing Analysis (STA) tools assume synchronous clock relationships and cannot analyze paths between asynchronous domains. CDC paths must be explicitly identified through timing constraints such as set_clock_groups -asynchronous or set_false_path to prevent the STA engine from reporting unclosable timing violations. However, simply declaring false paths does not guarantee functional correctness. Dedicated CDC verification tools (e.g., Siemens Questa CDC, Synopsys SpyGlass CDC) perform structural analysis to detect missing synchronizers, reconvergence of synchronized signals, and glitch-prone combinational logic in CDC paths. A robust CDC methodology requires both constraint-based exclusion and structural linting.

A critical CDC pitfall occurs when multiple synchronized signals from the same source domain reconverge in the destination domain. Even if each signal is individually synchronized, differences in synchronizer latency or metastability resolution time can cause the reconverged logic to sample an inconsistent combination of old and new values. Reconvergence errors are particularly insidious because they pass single-bit CDC checks but cause functional corruption. Mitigation strategies include:

• Gray coding to collapse multi-bit changes into single-bit transitions.
• Data bundling with a synchronized control signal that qualifies the data only after all bits are stable.
• CEA (Common Event Acknowledgement) handshake protocols that guarantee coherent transfer.