AXI4-Stream Interface

AXI4-Stream establishes a single-master to single-slave connection, creating a dedicated data highway that flows in one direction. This eliminates the arbitration overhead and shared bus contention found in memory-mapped interfaces.

• Master (Source): Drives data onto the bus (e.g., a predistorter core outputting corrected I/Q samples)
• Slave (Sink): Consumes data from the bus (e.g., a DAC interface or JESD204B framing block)
• No Address Phase: Unlike AXI4-Lite or AXI4-Full, there is no address channel, radically simplifying the handshake to a pure data flow

All data transfers are governed by a two-way hardware handshake using the TVALID and TREADY signals, enabling automatic backpressure and preventing data loss without software intervention.

• TVALID: Asserted by the master when valid data is present on TDATA
• TREADY: Asserted by the slave when it is ready to accept a new data word
• Transfer Occurs: Only on the rising clock edge when both TVALID and TREADY are asserted simultaneously
• Backpressure: If the slave de-asserts TREADY, the master must hold its data and wait, naturally stalling the pipeline

The core data payload is carried on TDATA, with critical sideband signals providing byte-level granularity and packet boundary delineation.

• TDATA: The primary data payload, typically a configurable width (e.g., 32, 64, 128 bits) carrying complex I/Q samples
• TKEEP: A byte-qualifier mask that indicates which bytes of TDATA contain valid data, essential for handling transfers that are not a multiple of the bus width
• TLAST: A marker asserted by the master on the final data beat of a packet or frame, allowing the slave to identify transaction boundaries without parsing the data stream
• TID/TDEST: Optional routing signals for managing multiple data streams over a shared physical interface

AXI4-Stream is the native protocol for high-level synthesis (HLS) dataflow functions, allowing predistorter cores to process samples with deterministic, minimal latency.

• No Buffering Overhead: Data flows directly from the predistorter's complex multiplier output to the DAC interface without intermediate DMA descriptors or shared memory copies
• Direct HLS Mapping: Vivado HLS automatically infers AXI4-Stream interfaces for function arguments declared as hls::stream<>, enabling a seamless path from C++ algorithm to RTL
• Deterministic Timing: The handshake-based flow control guarantees that a sample presented at the input appears at the output after a fixed number of clock cycles, critical for meeting the tight latency budgets of real-time DPD feedback loops

AXI4-Stream interfaces enable drag-and-drop connectivity in Xilinx's IP Integrator environment, allowing complex DPD signal chains to be assembled visually.

• Automatic Connection: IP Integrator recognizes AXI4-Stream master and slave ports and can auto-connect them with a single click
• Protocol Checking: The tool performs design rule checks to ensure TVALID/TREADY handshake compatibility and bus width matching
• Interconnect IP: AXI4-Stream Interconnect cores provide routing, arbitration, and width conversion for more complex topologies involving multiple predistorter channels or observation paths
• Example Chain: DPD Core (Master) → AXI4-Stream Broadcast → CFR Block → DAC Interface (Slave)

AXI4-Stream is fundamentally different from AXI4-Full and AXI4-Lite, trading random access for maximum throughput and minimum resource utilization.

• AXI4-Full: Memory-mapped, burst-capable, with separate read/write address channels. Used for processor-to-memory transactions. Overhead: 5 channels.
• AXI4-Lite: Simplified memory-mapped for control registers. Used for configuring DPD coefficients via a processor. Overhead: 5 channels, no bursts.
• AXI4-Stream: No address phase, single data channel. Used for the high-speed DPD forward and observation paths. Overhead: 1 channel.
• Resource Savings: Eliminating address logic and arbitration saves significant LUT and FF resources, which are then available for the predistorter's complex multipliers and FIR filter structures.

The TLAST signal marks the final data beat of a packet or frame, essential for block-based DSP operations in DPD systems. When a predistorter processes OFDM symbols or time-slot-based waveforms, TLAST delineates symbol boundaries, triggering downstream blocks to perform frame-level processing such as FFT windowing or cyclic prefix insertion. Without TLAST, receivers cannot distinguish between continuous streaming samples and structured communication frames, making it critical for 5G NR and LTE physical layer implementations.

The TDATA signal carries the actual payload, typically configured as multiples of 8 bits up to 1024 bits wide. For DPD applications, complex I/Q samples are commonly packed as 32-bit TDATA (16-bit I + 16-bit Q) or 64-bit TDATA (32-bit I + 32-bit Q) for high-resolution predistortion. Multi-sample packing—placing two or four complex samples on a wider bus—increases throughput without raising clock frequency, a technique used when the predistorter core operates at a lower rate than the JESD204B serial lanes driving the DAC.

Critical distinction for DPD architects: AXI4-Stream carries pure sequential data with no address concept, achieving maximum throughput with minimal logic. AXI4 Memory-Mapped (Full/Lite) uses address-based transactions for register configuration and buffer access. In a Zynq UltraScale+ DPD system, the processing system uses AXI4-Lite to write predistortion coefficients to control registers, while the actual I/Q sample stream flows through AXI4-Stream interfaces directly between the predistorter core and RFSoC DAC tiles, avoiding memory bottlenecks entirely.