ET-DPD for GaN PAs

GaN HEMTs suffer from electron trapping in surface states and buffer layers, causing slow drain current transients when the supply voltage changes rapidly. Under ET operation, these traps create a history-dependent gain modulation that cannot be captured by standard memory polynomial models.

• Requires models with sub-1 Hz to kHz memory time constants
• Augmented Volterra models must include exponential decay kernels to track trap state
• Trap state is a function of both instantaneous drain voltage and its recent history
• Failure to compensate results in pattern-dependent EVM degradation during symbol transitions

GaN PAs exhibit self-heating effects that shift the device's quiescent operating point as a function of recent signal history. Under ET, the instantaneous power dissipation varies dramatically with the supply voltage, creating a tight coupling between the RF envelope and junction temperature.

• Thermal time constants span microseconds to milliseconds
• Supply-dependent efficiency changes alter the heat dissipation profile dynamically
• Dual-input thermal models must accept both RF power and supply voltage as heat sources
• Thermal memory interacts multiplicatively with electrical memory, requiring cross-term kernels

GaN devices exhibit a strong nonlinear input capacitance (Cgs and Cgd) that varies with the instantaneous drain voltage. As the ET supply modulator sweeps the drain voltage, the device's phase shift changes dynamically, introducing supply-dependent AM/PM distortion that must be explicitly modeled.

• Phase distortion is a function of both input power and instantaneous Vdd
• Requires 3D LUT structures indexed by |x(n)| and Vdd(n)
• AM/PM conversion increases at low Vdd near the ET efficiency knee
• Critical for high-order QAM constellations sensitive to phase errors

GaN HEMTs have a sharper knee voltage transition compared to LDMOS, where the device rapidly moves from linear to saturation region. Under ET, the supply voltage frequently approaches this knee, causing abrupt gain collapse that creates high-order nonlinearities difficult to linearize with smooth polynomial basis functions.

• Requires piecewise or spline-based predistortion functions near the knee
• Shaping functions must avoid operating points below the knee for linearity-critical waveforms
• High-order Volterra kernels needed to capture the sharp curvature
• Interacts with ET modulator slew rate limitations to create clipping-induced distortion

GaN PAs typically operate over wider bandwidths than LDMOS, exposing frequency-dependent impedance interactions between the supply modulator output and the PA drain. The modulator's non-zero output impedance creates a voltage divider effect that varies with the RF envelope frequency, introducing frequency-selective supply distortion.

• Modulator output impedance interacts with PA drain decoupling network
• Creates envelope-frequency-dependent gain and phase ripple
• Requires joint ET-DPD models that include modulator dynamics
• Particularly severe for wideband 5G NR signals with 100+ MHz bandwidth

Unlike LDMOS which exhibits monotonic gain compression, GaN PAs often display a gain expansion region at moderate drive levels before entering compression. Under ET, this expansion characteristic shifts with supply voltage, creating non-monotonic AM-AM curves that require specialized basis functions beyond standard odd-order polynomials.

• Gain expansion can reach 1-2 dB before compression onset
• Expansion peak location shifts with Vdd, requiring 2D characterization
• Generalized memory polynomial models need even-order terms to capture asymmetry
• Critical for Doherty GaN PAs where carrier and peaking stages interact

GaN HEMTs exhibit charge trapping at surface states and buffer layers, causing slow drain current transients (gate-lag and drain-lag) that manifest as long-term memory effects. Under ET, the dynamic drain voltage modulates these trap states, creating a complex, history-dependent nonlinearity.

• Modeling: Requires advanced kernel functions in Volterra series or recurrent neural network layers to capture sub-threshold time constants.
• Correction: DPD must include terms sensitive to the envelope history over milliseconds, not just instantaneous power.
• Impact: Uncorrected trapping causes significant ACLR degradation and packet-dependent EVM drift in TDD systems.

GaN-on-SiC PAs exhibit rapid dynamic self-heating under bursty ET waveforms. The channel temperature modulates electron mobility and threshold voltage, introducing a thermally-induced nonlinear memory that interacts with the electrical memory of the matching network.

• Dual-Memory Problem: DPD must decouple fast electrical memory (ns) from slower thermal memory (µs-ms).
• ET Interaction: Supply voltage modulation directly controls instantaneous power dissipation, making thermal transients a function of the shaping table.
• Modeling Approach: Augmented behavioral models often include a low-pass filtered power term as a proxy for junction temperature.

A memoryless predistortion structure indexed by instantaneous input power and instantaneous supply voltage. This 3D LUT directly maps the complex gain correction required for the static nonlinearity of a GaN ET PA.

• Structure: Address is (|x(n)|, Vdd(n)), output is a complex gain word G(|x|, Vdd).
• Adaptation: Table entries are updated using a least-mean-squares (LMS) or recursive least-squares (RLS) algorithm based on the observed residual distortion.
• Limitation: Purely static; must be cascaded with a memory polynomial to handle GaN trapping and thermal effects.

A single, unified behavioral model that simultaneously captures the nonlinear dynamics of both the GaN PA and the supply modulator. This avoids the error accumulation of cascading separate models.

• Inputs: Baseband I/Q signal and the target envelope voltage.
• Output: Predicted RF output, including artifacts from modulator slew-rate limiting and ripple.
• Structure: Often implemented as a dual-input neural network or a deeply augmented Volterra series where modulator dynamics are folded into the basis functions.
• Advantage: Enables a single predistorter to compensate for the entire transmitter line-up, simplifying FPGA implementation.