ET-DPD for 5G NR

5G NR signals feature component carrier bandwidths up to 100 MHz (FR1) and 400 MHz (FR2), requiring DPD linearization bandwidths of 400–800 MHz to capture fifth-order intermodulation products. The ET-DPD system must operate at sampling rates exceeding 1.2 GSPS to satisfy Nyquist criteria for the predistorted signal. This demands high-speed data converters and FPGA-based processing pipelines capable of real-time coefficient computation across the full instantaneous bandwidth.

5G NR OFDM signals exhibit PAPR values of 10–13 dB, significantly stressing both the power amplifier and the envelope tracking supply modulator. The ET-DPD system must linearize the PA across its full dynamic range while the shaping function simultaneously maps instantaneous envelope power to drain voltage. Crest factor reduction (CFR) is often co-optimized with ET-DPD to prevent supply modulator clipping on extreme peaks, balancing efficiency against EVM degradation.

Unlike fixed-supply DPD, ET-DPD requires a dual-input model that accepts both the RF baseband signal and the instantaneous supply voltage as independent variables. Architectures such as the Augmented Volterra series or 3D Look-Up Tables (3D LUTs) indexed by |x(n)| and Vdd(n) capture the supply-dependent gain compression and ET-induced AM/PM distortion. The model must characterize the PA's behavior across the entire two-dimensional operating space to invert the composite nonlinearity.

5G NR mandates EVM limits as low as 3.5% for 256-QAM and 1.5% for 1024-QAM modulation schemes, alongside stringent adjacent channel leakage ratios (ACLR) typically exceeding 45 dBc. ET-DPD must simultaneously suppress spectral regrowth into adjacent channels while maintaining modulation accuracy. The joint optimization of linearity and efficiency requires iterative training of the predistorter across multiple supply voltage trajectories to guarantee conformance across all resource block allocations.

Timing mismatch between the RF signal path and the envelope tracking supply voltage path at the PA transistor drain causes severe nonlinear distortion that cannot be corrected by memoryless DPD alone. For 5G NR wideband signals, sub-nanosecond alignment accuracy is required. The ET-DPD system must incorporate delay estimation and compensation algorithms, often using fractional-delay filters, to synchronize the two paths before the predistorter training sequence begins.

ET system behavior drifts with temperature, frequency, load impedance, and aging. Closed-loop ET-DPD architectures employ an observation receiver to capture the PA output and continuously update predistortion coefficients using algorithms such as recursive least squares (RLS) or least mean squares (LMS). For 5G NR TDD frames, training must occur within guard periods or during active transmission using decision-directed techniques, requiring rapid convergence within microseconds.

A joint optimization methodology where the digital predistortion algorithm and the envelope tracking supply modulator are engineered concurrently. This approach manages the compounded nonlinearities of the combined system rather than treating them as independent problems.

• Enables higher overall system efficiency than sequential design
• Requires a unified simulation framework combining PA, modulator, and DPD models
• Critical for meeting 5G NR EVM requirements at high power levels

Unwanted phase modulation of the output RF signal caused by the dynamic variation of the power amplifier's supply voltage. As the drain voltage changes to track the envelope, the PA's input capacitance varies nonlinearly, shifting the signal phase.

• A primary source of residual distortion in ET systems
• Requires memory-capable DPD models to compensate
• Particularly severe in GaN HEMT devices due to trapping effects

A power amplifier modeling framework that accepts both the RF input signal and the dynamic supply voltage as independent variables. This structure is essential for accurately predicting the nonlinear behavior of an envelope tracking PA.

• Output is a function: y(n) = f(x(n), Vdd(n))
• Enables separate characterization of supply-dependent gain compression
• Forms the basis for 3D LUT and augmented Volterra predistorters

The precise time-synchronization of the RF signal path and the envelope tracking supply voltage path at the power amplifier's transistor drain. A mismatch as small as hundreds of picoseconds can cause severe distortion.

• Misalignment creates intermodulation products that degrade ACLR
• Requires calibration using cross-correlation techniques in the feedback path
• Delay drifts with temperature, necessitating adaptive tracking loops

An extension of the Volterra series behavioral model that incorporates dynamic supply voltage terms. This captures the complex nonlinear interactions and memory effects specific to envelope tracking power amplifiers.

• Adds cross-kernel terms coupling input and supply voltage histories
• Model complexity grows rapidly; requires pruning algorithms for implementation
• Provides the theoretical foundation for many ET-aware DPD structures

The maximum rate of change of the supply modulator's output voltage, typically measured in V/µs. It must be high enough to accurately reproduce the fast-rising envelope of wideband 5G NR signals without introducing tracking errors.

• Insufficient slew rate causes clipping distortion on signal peaks
• 100 MHz NR carriers demand slew rates exceeding 100 V/µs
• A key specification driving multi-phase buck converter and hybrid modulator designs