Inferensys

Glossary

ET-DPD Co-Design

A joint optimization methodology where the digital predistortion linearization algorithm and the envelope tracking supply modulator are designed concurrently to manage the compounded nonlinearities of the combined system.
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JOINT OPTIMIZATION METHODOLOGY

What is ET-DPD Co-Design?

ET-DPD co-design is a holistic transmitter optimization methodology where the digital predistortion linearization algorithm and the envelope tracking supply modulator are engineered concurrently to jointly manage the compounded nonlinearities of the combined system.

ET-DPD co-design is a joint optimization methodology where the digital predistortion (DPD) linearization algorithm and the envelope tracking (ET) supply modulator are designed concurrently, rather than sequentially, to manage the compounded nonlinearities of the combined system. This approach recognizes that the dynamic supply voltage from the ET modulator and the RF input signal interact within the power amplifier (PA) to produce distortion that cannot be effectively corrected by independently designed subsystems.

The co-design process involves developing a unified dual-input behavioral model that captures the PA's response to both RF input and instantaneous drain voltage, including ET-induced AM/PM distortion and supply-dependent gain compression. By jointly optimizing the shaping function, modulator slew rate, and DPD coefficient extraction, engineers achieve superior adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) while maximizing overall system power-added efficiency (PAE).

JOINT OPTIMIZATION METHODOLOGY

Key Characteristics of ET-DPD Co-Design

A systematic framework where the digital predistortion linearization algorithm and the envelope tracking supply modulator are designed concurrently to manage the compounded nonlinearities of the combined system.

01

Unified Nonlinearity Compensation

ET-DPD co-design addresses the compounded distortion arising from the interaction of the power amplifier's native nonlinearity and the supply modulator's dynamic behavior. Rather than treating these as separate problems, a joint behavioral model captures the cross-dependencies between RF input, supply voltage, and output distortion.

  • Compensates for ET-induced AM/PM distortion caused by supply-dependent phase shifts
  • Corrects supply modulator nonlinearity including slew-rate limiting and switching ripple artifacts
  • Accounts for supply-dependent gain compression across the full dynamic voltage range
  • Eliminates the need for separate PA linearizer and ET compensator blocks
02

Dual-Input Behavioral Modeling

The foundation of ET-DPD co-design is the dual-input behavioral model, which accepts both the baseband RF signal and the instantaneous supply voltage as independent variables. This enables the predistorter to predict the PA's output as a function of both excitation dimensions.

  • Augmented Volterra series extend classical memory polynomial models with supply voltage terms
  • 3D Look-Up Tables (3D LUTs) index correction coefficients by both input power and supply voltage
  • Models capture cross-term memory effects where past supply voltages influence current RF behavior
  • Enables accurate prediction of output under arbitrary shaping function trajectories
03

Shaping Function Co-Optimization

In ET-DPD co-design, the shaping function that maps signal envelope to supply voltage is not designed in isolation. It is jointly optimized with the DPD coefficients to find the Pareto-optimal trade-off between efficiency and linearizability.

  • Iso-gain contour analysis identifies supply voltage trajectories that maintain constant gain
  • Shaping functions are designed to avoid regions of high AM/PM sensitivity that are difficult to linearize
  • Crest factor reduction (CFR) is co-optimized to prevent supply modulator overdrive from extreme peaks
  • The shaping function becomes a tunable parameter in the overall linearization optimization loop
04

ET-Aware DPD Training

Conventional DPD training assumes a fixed supply voltage. ET-aware training excites the PA across its full dynamic supply range during coefficient extraction, ensuring the predistorter generalizes to all tracking conditions.

  • Training signals must span the entire supply voltage range and envelope bandwidth
  • Closed-loop adaptation continuously updates coefficients to track thermal and aging effects
  • Training data captures envelope-bandwidth mismatch scenarios where the modulator cannot perfectly track
  • Coefficients are validated across multiple shaping functions to ensure robustness to ET parameter changes
05

Delay Alignment and Synchronization

A critical aspect of ET-DPD co-design is the precise time-alignment of the RF signal path and the envelope tracking supply path at the transistor drain. Misalignment by even fractions of a nanosecond causes severe distortion that no predistorter can correct.

  • ET delay alignment must be maintained within tens of picoseconds for wideband signals
  • Co-design incorporates digital delay compensation in the baseband processing chain
  • Joint optimization accounts for group delay variations in both the RF and supply modulator paths
  • Adaptive delay tracking compensates for temperature-dependent propagation changes
06

System-Level Efficiency Metrics

ET-DPD co-design optimizes for total system power added efficiency (PAE), not just the PA's standalone efficiency. This holistic metric accounts for the power consumed by the supply modulator, the DPD processing, and the feedback receiver.

  • System PAE = (RF output power - RF input power) / (PA DC power + modulator DC power + DPD compute power)
  • Co-design identifies the ET efficiency knee where further supply modulation yields diminishing returns
  • Trade-offs between linearization complexity (gate count, power) and achievable efficiency are explicitly modeled
  • Optimization targets include 5G NR spectral mask compliance and error vector magnitude (EVM) requirements simultaneously
ET-DPD CO-DESIGN

Frequently Asked Questions

Expert answers to critical questions about the joint optimization of envelope tracking power supplies and digital predistortion linearization for next-generation wireless transmitters.

ET-DPD co-design is a joint optimization methodology where the digital predistortion linearization algorithm and the envelope tracking supply modulator are developed concurrently rather than independently. This approach is necessary because the dynamic supply voltage modulation in an ET system introduces compounded nonlinearities that cannot be adequately corrected by a DPD designed in isolation. When a power amplifier's drain voltage varies with the signal envelope, it generates supply-dependent gain compression, ET-induced AM/PM distortion, and complex memory effects that interact with the modulator's own bandwidth limitations and nonlinearities. A co-designed system models the entire transmitter chain—including the shaping function, supply modulator dynamics, and PA behavior under varying drain voltages—as a single unified system, enabling the predistorter to learn and invert the complete nonlinear transfer function rather than treating each subsystem separately.

ET-DPD INTEGRATION METHODOLOGY

Sequential vs. Co-Design Approach

Comparison of traditional sequential design and concurrent co-design methodologies for integrating envelope tracking power supplies with digital predistortion linearization

FeatureSequential DesignET-DPD Co-Design

Design Philosophy

ET modulator and DPD developed independently, then integrated

ET modulator and DPD optimized concurrently as a unified system

Nonlinearity Modeling

Separate PA model and modulator model; interactions approximated

Single joint model capturing PA-modulator interactions and compounded nonlinearities

ET-Induced AM/PM Compensation

Supply Modulator Nonlinearity Correction

Shaping Function Optimization

Static LUT designed for efficiency only

Jointly optimized with DPD coefficients for linearity-efficiency trade-off

Development Timeline

Longer; iterative rework during integration phase

Shorter; concurrent development eliminates integration surprises

System PAE Improvement

5-8% over fixed supply

10-15% over fixed supply

ACLR Compliance Margin

2-3 dB margin typical

5-8 dB margin typical

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.