Inferensys

Glossary

ET Delay Alignment

The precise time-synchronization of the RF signal path and the envelope tracking supply voltage path at the power amplifier's transistor drain to prevent severe distortion caused by timing mismatch.
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ENVELOPE TRACKING SYNCHRONIZATION

What is ET Delay Alignment?

ET delay alignment is the precise time-synchronization of the RF signal path and the envelope tracking supply voltage path at the power amplifier's transistor drain to prevent severe distortion caused by timing mismatch.

ET delay alignment is the critical process of matching the propagation delay between the RF signal path and the envelope tracking supply modulator path so that the dynamic drain voltage arrives at the power amplifier's transistor precisely when the corresponding RF envelope peak does. A misalignment of even a few nanoseconds causes the supply voltage to be too high or too low for the instantaneous RF amplitude, resulting in severe spectral regrowth, degraded error vector magnitude (EVM), and potential violation of adjacent channel leakage ratio (ACLR) masks.

Alignment is typically achieved through a combination of baseband digital delay buffers and physical trace-length matching on the printed circuit board. The digital predistortion system must be trained after alignment is calibrated, as the ET-induced AM/AM and AM/PM distortion profiles are highly sensitive to timing skew. Advanced implementations use adaptive delay estimation algorithms that cross-correlate the transmitted RF envelope with the observed supply voltage ripple at the feedback receiver to continuously track and correct for temperature-dependent delay drift.

TIME SYNCHRONIZATION

Key Characteristics of ET Delay Alignment

The precise alignment of the RF signal path and the envelope tracking supply voltage path at the power amplifier's transistor drain. Even nanosecond-scale mismatches cause severe spectral regrowth and degrade error vector magnitude (EVM).

01

Path Delay Mismatch

The fundamental problem where the RF envelope signal and the dynamic supply voltage arrive at the PA drain at different times. This mismatch creates a window where the supply voltage is either too high (wasting power) or too low (clipping the RF waveform). Typical tolerances are on the order of ±1 ns for wideband 5G signals, requiring sub-nanosecond calibration precision.

< 1 ns
Required Alignment Tolerance
02

AM-AM and AM-PM Distortion Signatures

Delay misalignment produces characteristic distortion signatures:

  • AM-AM Distortion: The output amplitude deviates from the expected value because the PA gain is modulated by the wrong instantaneous supply voltage.
  • AM-PM Distortion: The phase shift through the PA varies with supply voltage; a delayed supply modulates the phase at the wrong instant, causing unwanted phase modulation. These signatures are distinct from static PA nonlinearity and require delay-aware DPD models.
03

Delay Estimation Techniques

Accurate delay measurement is critical. Common methods include:

  • Cross-Correlation: Correlating the baseband IQ envelope with the sensed supply voltage waveform to find the peak correlation lag.
  • Fractional Delay Interpolation: Using Farrow structures or polyphase filters to achieve sub-sample delay resolution beyond the digital clock period.
  • Model-Based Estimation: Iteratively fitting a behavioral model that includes a delay parameter and minimizing the model error.
04

Hardware Alignment Methods

Physical implementation strategies for achieving alignment:

  • Programmable Delay Lines: Digitally controlled delay elements inserted in either the RF or envelope path to compensate for fixed skew.
  • Baseband Buffer Management: Adjusting the relative timing of digital samples in the transmit datapath before digital-to-analog conversion.
  • Matched Trace Routing: Careful PCB layout to equalize the electrical length of the RF and envelope supply traces, minimizing the initial skew that must be corrected.
05

Impact on DPD Performance

Delay misalignment directly degrades the effectiveness of the digital predistorter. If the DPD model assumes the supply voltage is aligned but it is not, the predistorter learns an incorrect inverse function. This results in:

  • Incomplete cancellation of spectral regrowth
  • Elevated Adjacent Channel Leakage Ratio (ACLR)
  • Degraded Error Vector Magnitude (EVM) Joint estimation of delay and DPD coefficients is often required for robust performance.
06

Temperature and Aging Drift

The relative delay between the RF and envelope paths is not static. It drifts over time due to:

  • Thermal expansion of PCB materials and cables
  • Component aging affecting analog group delay in filters and amplifiers
  • Voltage-dependent capacitance in the supply modulator Adaptive delay tracking loops are necessary in deployed systems to maintain alignment over the product lifetime without manual recalibration.
ET DELAY ALIGNMENT

Frequently Asked Questions

Precision timing is the critical foundation of any envelope tracking system. Explore the most common questions about synchronizing the RF envelope and dynamic supply voltage to prevent catastrophic linearity degradation.

ET delay alignment is the precise time-synchronization of the RF signal path and the envelope tracking supply voltage path at the power amplifier's transistor drain. It ensures that the dynamic supply voltage arrives at the exact moment the corresponding RF envelope peak reaches the transistor. A misalignment of even a few nanoseconds causes the supply voltage to be too low during an RF peak—clipping the signal—or too high during a trough—wasting power and introducing AM/PM distortion. This timing mismatch is the single most severe source of nonlinear distortion in an ET system, often degrading adjacent channel leakage ratio (ACLR) by 10–15 dB and completely negating the linearity benefits of digital predistortion. Without precise alignment, the ET system introduces more distortion than it solves, making it the foundational calibration step before any DPD coefficient extraction can occur.

Prasad Kumkar

About the author

Prasad Kumkar

CEO & MD, Inference Systems

Prasad Kumkar is the CEO & MD of Inference Systems and writes about AI systems architecture, LLM infrastructure, model serving, evaluation, and production deployment. Over 5+ years, he has worked across computer vision models, L5 autonomous vehicle systems, and LLM research, with a focus on taking complex AI ideas into real-world engineering systems.

His work and writing cover AI systems, large language models, AI agents, multimodal systems, autonomous systems, inference optimization, RAG, evaluation, and production AI engineering.