Trap Effects

A transient drain current reduction following a gate voltage step, caused by surface acceptor-like traps in the gate-drain access region. When the gate is pinched off, electrons are captured by surface states, creating a virtual gate extension that depletes the channel. Upon gate turn-on, these trapped electrons are slowly emitted with time constants ranging from microseconds to seconds, causing the drain current to recover gradually rather than instantaneously. This introduces a low-frequency pole in the amplifier's transfer function, degrading the linearity of signals with varying envelope amplitudes.

A slow transient in drain current following a drain voltage step, primarily attributed to buffer layer traps and deep-level defects in the epitaxial structure. When the drain voltage increases abruptly, electrons are injected into trap states within the Fe-doped or C-doped buffer layer beneath the two-dimensional electron gas channel. These trapped electrons electrostatically deplete the channel from below, reducing the sheet carrier density. The subsequent slow de-trapping process creates a history-dependent knee voltage walkout and gain modulation that manifests as long-term memory effects in the amplifier's nonlinear response.

A phenomenon where the dynamic on-resistance of a GaN HEMT increases significantly after exposure to high drain bias stress, reducing the maximum available drain current compared to DC characteristics. Current collapse is the cumulative manifestation of both gate lag and drain lag acting simultaneously. During large-signal RF operation, the peak drain voltage swing repeatedly populates trap states, causing the instantaneous knee voltage to increase and the saturated current to decrease. This creates a compression of the load line that varies with the signal's recent envelope history, introducing complex nonlinear memory that cannot be corrected by memoryless predistortion alone.

The frequency-dependent separation between the amplifier's DC I-V characteristics and its RF dynamic load line, caused by the inability of trapped charge to respond instantaneously to the RF envelope. At high modulation frequencies, traps cannot follow the instantaneous signal variations, but they do respond to the slower-varying envelope power. This creates a dispersion between the low-frequency and high-frequency gain and phase responses. In two-tone and modulated signal tests, this manifests as asymmetric intermodulation distortion sidebands and a frequency-dependent AM-AM/AM-PM characteristic that violates the static nonlinearity assumption underlying many behavioral models.

The capture and emission kinetics of trap states are characterized by distributed time constants spanning many orders of magnitude, from nanoseconds to minutes. This wide distribution arises from the spatial dispersion of trap energy levels within the bandgap and the tunneling-assisted nature of carrier capture in high-field regions. The multi-exponential transient response is often modeled using:

• Stretched exponential functions for dispersive transport
• Multiple discrete RC time constants for circuit-oriented models
• Volterra kernels with long memory tails for behavioral DPD models Accurate characterization requires pulsed I-V measurements with varying quiescent bias points and pulse widths to isolate individual trap signatures.

Trap-induced memory effects fundamentally limit the linearization bandwidth and correction capability of digital predistortion systems. Because trapping introduces nonlinear dynamics that depend on the signal's long-term envelope history, conventional memory polynomial models with finite memory depth cannot fully capture the dispersion. This results in:

• Residual ACLR floor that cannot be reduced by increasing DPD model complexity alone
• EVM degradation in wideband signals with high PAPR
• Temperature-dependent trapping behavior requiring adaptive model updates Advanced mitigation strategies include trap-aware Volterra models, deep neural network DPD with recurrent layers to capture long time constants, and device-level epitaxial engineering to minimize trap density.

A transient drain current suppression following a gate voltage step from pinch-off to the on-state. In GaN HEMTs, surface or barrier traps capture electrons when the gate is reverse-biased, creating a virtual gate that depletes the channel. When the gate switches on, these traps release slowly (microseconds to seconds), causing the drain current to recover gradually rather than instantaneously. This introduces low-frequency dispersion in the I-V characteristics and degrades the amplifier's ability to track fast envelope variations in modern communication signals.

A transient reduction in drain current following a high drain voltage stress event. When the drain is subjected to large-signal voltage swings, electrons are injected into buffer or substrate traps beneath the channel. These trapped charges create a back-gating effect that partially depletes the two-dimensional electron gas (2DEG), reducing the instantaneous current. After the high-voltage stress is removed, the traps emit slowly, causing a gradual current recovery. Drain lag is a primary contributor to long-term memory effects in Doherty amplifiers, where the peaking amplifier experiences extreme voltage excursions.

The frequency-dependent variation in a transistor's transconductance (gm) and output conductance (gds) caused by trap states with long time constants. At DC or low frequencies, traps can follow the signal and modulate the channel charge, altering the effective I-V relationship. At RF frequencies above the trap emission rate, traps remain in a quasi-static state, and the device exhibits a different, typically higher, dynamic current. This discrepancy between DC I-V and RF load-line behavior complicates amplifier design and necessitates trap-aware behavioral models for accurate digital predistortion.

A measurement methodology using pulsed I-V with varying quiescent bias points to isolate and quantify trap-related dispersion. By pulsing from different gate and drain quiescent voltages (Vgsq, Vdsq) into the same measurement point, the impact of trapping can be separated from self-heating effects. The difference between a 'cold' pulse (no trapping, no heating) and a 'hot' pulse (trapping and heating present) reveals the magnitude of trap-induced current collapse. This data is essential for extracting trap time constants and building accurate nonlinear models.

The temporary reduction in maximum saturated drain current (Idss) following a high-voltage stress condition, representing the combined effect of gate lag and drain lag. Current collapse degrades the amplifier's peak output power and efficiency, particularly in the peaking amplifier of a Doherty configuration where large voltage swings are routine. Mitigation strategies include field plate engineering, surface passivation, and epitaxial layer optimization to minimize trap density. From a linearization perspective, current collapse introduces a signal-history-dependent gain compression that must be captured by the predistorter's memory model.

The characteristic emission and capture rates of trap states, typically spanning from nanoseconds to seconds, that dictate the frequency range over which memory effects manifest. Fast traps (ns–µs) affect intra-pulse envelope tracking, while slow traps (ms–seconds) cause inter-pulse or frame-level memory. Accurate extraction of these time constants via multi-pulse characterization or random telegraph signal (RTS) noise analysis enables the development of physics-based trap models. These models inform the memory depth requirements of the digital predistortion algorithm, ensuring the DPD can compensate for both short-term and long-term dispersion.