Post-Matching Doherty

Unlike the conventional architecture where matching occurs before the combiner, post-matching places dedicated impedance matching networks directly at the output of each carrier and peaking transistor. This isolates the intrinsic device parasitics from the combining node, presenting optimized fundamental and harmonic terminations to each device independently.

• Enables precise harmonic termination for each transistor to shape current and voltage waveforms
• Reduces interaction between the device's knee voltage effects and the impedance inverter
• Simplifies the design of the subsequent Doherty combiner network

By absorbing the transistor's output capacitance and package parasitics into the post-matching network, the impedance inverter (typically a quarter-wave transmission line) operates on well-defined, real impedance terminations. This eliminates the need for complex, offset-line tuning at the combiner input.

• The inverter transforms a pure resistance rather than a complex, frequency-dependent impedance
• Reduces the sensitivity of load modulation to frequency variation
• Enables the use of simpler, more compact inverter structures

The decoupling of device matching from the combiner network is the primary enabler of broadband Doherty operation. The post-matching architecture maintains consistent back-off efficiency and load modulation across fractional bandwidths exceeding 40%, a critical requirement for multi-band 5G base stations.

• Mitigates the frequency dispersion of the impedance inverter's electrical length
• Maintains the correct phase alignment between branches over a wider frequency range
• Reduces gain mismatch variation across the operating band, easing the burden on the digital predistortion system

The topology allows the carrier amplifier (Class-AB) and peaking amplifier (Class-C) to be matched to their distinct optimal impedances without mutual constraint. This is particularly advantageous in asymmetric Doherty designs where the peaking transistor is significantly larger.

• The carrier can be matched for peak efficiency at back-off, while the peaking is matched for maximum saturated power
• Facilitates the use of different transistor technologies or gate peripheries in each branch
• Enables independent AM-PM distortion pre-compensation through tailored matching

By isolating the sensitive device-plane matching from the high-power combining network, the post-matching architecture exhibits greater robustness to PCB fabrication variations and component tolerances. The well-defined impedances at the combiner inputs result in more predictable, repeatable load modulation behavior in mass production.

• Less performance variation due to substrate dielectric constant changes
• Reduced post-assembly tuning requirements on the production line
• More consistent adjacent channel leakage ratio (ACLR) performance across units

The post-matching topology is a foundational enabler for Broadband Doherty designs. By placing individual matching networks after the transistors, the frequency-dependent behavior of the impedance inverter is simplified, allowing for consistent load modulation and high back-off efficiency across a much wider continuous frequency range than traditional single-stage matching approaches.

A core advantage of post-matching is the simplification of the impedance inverter design. The post-matching network transforms the standard 50-ohm system impedance to a lower, optimal level for the combiner. This allows the inverter, often a quarter-wave line, to operate at a fixed, real impedance ratio, eliminating complex wideband compensation and making the Doherty combiner more compact and less lossy.

Precise phase alignment between the carrier and peaking paths is critical for constructive power combining at the output. In a post-matching design, the individual matching networks must be carefully co-designed with the combiner to ensure that the signals arrive in-phase at the summing node. Any gain mismatch or phase error directly degrades power-added efficiency (PAE) and increases the linearization burden.

The post-matching network provides a strategic location to engineer harmonic terminations. By presenting specific short-circuit or open-circuit impedances at the second and third harmonic frequencies to the transistor's intrinsic current source, designers can shape the voltage and current waveforms for Class-F or inverse Class-F operation. This further enhances efficiency beyond what load modulation alone can achieve.

Designing a post-matching Doherty relies heavily on load-pull analysis. Engineers use large-signal measurements, including hot S22 parameters, to map the optimal impedance trajectories for the carrier and peaking transistors across power levels. This data directly informs the synthesis of the post-matching network to ensure the correct impedances are presented for maximum efficiency and linearity at a given output back-off (OBO).

While the post-matching topology primarily addresses bandwidth, it must coexist with techniques to manage memory effects. The individual matching networks can influence low-frequency baseband impedance, which is critical for mitigating self-heating and trap effects in GaN HEMT devices. Proper design minimizes these dynamic nonlinearities, reducing the complexity required of the digital predistortion (DPD) system.