Load-Pull Analysis

Load-pull systematically varies the impedance presented to the device under test (DUT) at the fundamental frequency by controlling a tuner's reflection coefficient magnitude and phase. At each impedance point, the DUT's output power, gain, efficiency, and linearity are measured. The resulting data is plotted as contours on a Smith chart, revealing the impedance regions that maximize specific performance metrics. This technique directly accounts for the large-signal nonlinear behavior of transistors, which cannot be predicted from small-signal S-parameters alone.

Two distinct architectures exist for synthesizing load impedances:

• Passive load-pull uses a mechanical or electronic tuner to reflect a portion of the incident wave, limited to reflection coefficients within the tuner's loss circle (typically |Γ| < 0.9).
• Active load-pull injects a coherent signal into the DUT output through a directional coupler, enabling synthesis of arbitrary impedances including |Γ| = 1 (pure reactance) and even negative resistance regions.
• Hybrid load-pull combines both techniques, using passive tuning for coarse impedance setting and active injection to overcome fixture losses at high frequencies.

Extending load-pull beyond the fundamental frequency, harmonic load-pull independently controls impedances at the 2nd and 3rd harmonic frequencies (2f₀ and 3f₀). This enables characterization of waveform engineering techniques where harmonic terminations shape the transistor's intrinsic voltage and current waveforms. Proper harmonic tuning can achieve Class-F, inverse Class-F, or Class-J operation, significantly boosting power-added efficiency. Modern systems use multi-harmonic active tuners to present independent, calibrated impedances at f₀, 2f₀, and 3f₀ simultaneously.

The complementary technique to load-pull, source-pull varies the impedance presented at the input of the DUT. This is critical for optimizing gain, noise figure, and input match under large-signal drive conditions. In power amplifier design, source-pull identifies the impedance that maximizes transducer gain while maintaining stability. Combined source-load-pull sweeps both input and output impedances simultaneously, mapping the full two-port large-signal operating space to identify the global optimum for a given performance trade-off.

Load-pull is indispensable for Doherty amplifier development:

• Carrier amplifier characterization at the design back-off power level identifies the high-efficiency impedance region where the carrier operates before peaking activation.
• Peaking amplifier characterization at peak power determines the optimal load for maximum saturated output.
• Active load-pull emulation simulates the dynamic impedance modulation that occurs as the peaking amplifier injects current, validating the Doherty combiner design before physical prototyping.
• Modulated load-pull uses wideband signals (e.g., 100 MHz 5G NR) to assess linearity and memory effects under realistic dynamic impedance conditions.

Modern load-pull systems employ vector receivers that capture both magnitude and phase of incident and reflected waves at the DUT reference plane. This enables:

• Waveform measurements of time-domain voltage and current at the transistor's current generator plane.
• Real-time load-pull where impedance is swept continuously while capturing full vector data, dramatically reducing measurement time.
• Polyharmonic distortion modeling by extracting the complex relationships between fundamental and harmonic components.
• AM-AM and AM-PM extraction at each impedance point, building comprehensive nonlinear behavioral models for digital predistortion development.

A graphical tool for solving transmission line and impedance matching problems. In load-pull analysis, the Smith chart is the universal coordinate system for plotting constant-power contours, constant-efficiency contours, and impedance trajectories. It maps all possible complex reflection coefficients (Γ) to a normalized impedance plane, allowing designers to visualize the optimal impedance region for trade-offs between PAE, output power, and linearity.

Closed-loop loci on the Smith chart representing the set of load impedances that deliver a specific output power level from the device under test. These contours are generated by systematically varying the load impedance using a vector network analyzer and an automated tuner. The innermost contour typically represents the maximum saturated power, while outer contours show power back-off levels. Designers use these to select impedances that balance power delivery with efficiency.

Loci of load impedances that yield a constant Power-Added Efficiency value. These contours rarely align perfectly with maximum power contours, creating the fundamental linearity-efficiency trade-off. Load-pull analysis reveals the impedance region where PAE peaks, which is often at a different reflection coefficient than the maximum power point. For Doherty designs, these contours guide the selection of the optimal back-off impedance for the carrier amplifier.

The complementary technique to load-pull where the source impedance presented to the device input is varied while measuring output performance. Source-pull maps the optimal input matching condition for maximum gain, minimum noise figure, or best linearity. In power amplifier design, source-pull is critical for determining the conjugate match that maximizes transducer gain while ensuring stability across the operating bandwidth.

An advanced load-pull technique that uses an active signal injection path to synthesize reflection coefficients with magnitudes approaching unity (|Γ| ≈ 1). Unlike passive mechanical tuners limited by fixture losses, active load-pull can present impedances near the edge of the Smith chart, essential for characterizing high-power transistors with very low knee voltage. This method enables precise mapping of the voltage and current waveforms for harmonic tuning.

Large-signal scattering parameters measured under nominal drive and bias conditions, as opposed to small-signal Cold S-parameters measured with the device unbiased. Hot S22, the large-signal output reflection coefficient, is critical for designing the Doherty combiner network. Using cold S-parameters for matching network design leads to significant errors because the device's output impedance changes dramatically under large-signal excitation due to nonlinear capacitances and current clipping.