Asymmetric Doherty

The defining characteristic of an asymmetric Doherty is its ability to maintain high power-added efficiency (PAE) at output back-off (OBO) levels significantly deeper than 6 dB. By using a peaking amplifier with a larger transistor periphery—typically 1.5x to 2x the carrier's size—the first efficiency peak shifts to:

• 9 dB OBO for a 1:1.5 carrier-to-peaking ratio
• 12 dB OBO for a 1:2 carrier-to-peaking ratio

This directly accommodates the high PAPR of 5G NR and OFDM signals without sacrificing average efficiency.

In a symmetric Doherty, the carrier and peaking amplifiers contribute equal maximum current at saturation. In an asymmetric design, the peaking amplifier delivers 1.5x to 2x the current of the carrier. This higher peaking current is essential for achieving the deeper load modulation required for extended back-off.

The fundamental load modulation equation becomes:

• At peak power: both amplifiers see their optimal impedance for maximum output
• At back-off: the carrier sees a higher transformed impedance, maintaining voltage swing and efficiency
• The transition point shifts based on the current ratio (α) between the two paths

The Doherty combiner requires careful impedance inverter design to accommodate the asymmetric current ratio. The characteristic impedance of the quarter-wave transformer must be scaled according to:

• The optimal load impedance of the carrier amplifier at peak power
• The current contribution ratio from the peaking path
• The desired back-off efficiency peak location

Post-matching networks are often employed after each amplifier to present the correct harmonic terminations and simplify the combiner design, especially in broadband asymmetric Doherty implementations.

Asymmetric designs introduce additional phase alignment challenges due to the different transistor sizes and potentially different input capacitances of the carrier and peaking devices. The input splitter must provide:

• Unequal power division matching the asymmetric drive requirements
• Precise phase offset to compensate for different electrical lengths in each branch
• Gate bias sequencing to ensure the Class-C peaking amplifier activates at the correct envelope threshold

Misalignment causes degraded AM-AM and AM-PM distortion, increasing the burden on the digital predistortion (DPD) linearization system.

While asymmetric Doherty amplifiers extend efficiency, they inherently exhibit more complex nonlinear behavior than symmetric designs. The larger peaking device introduces:

• Sharper gain expansion at the turn-on transition point
• Increased AM-PM distortion due to the nonlinear input capacitance of the larger Class-C biased peaking transistor
• Stronger memory effects from the asymmetric thermal profiles of the two devices

These characteristics demand advanced digital predistortion with generalized memory polynomial or neural network models capable of capturing the asymmetric nonlinear dynamics.

Gallium Nitride (GaN) HEMT technology is the preferred semiconductor platform for asymmetric Doherty designs due to:

• High power density enabling compact asymmetric layouts with significant size disparity between carrier and peaking transistors
• Low knee voltage maximizing voltage swing and efficiency at deep back-off
• Soft compression characteristics that are more amenable to linearization than the hard saturation of LDMOS
• Superior thermal conductivity on SiC substrates managing the asymmetric heat distribution

GaN's inherent linearity advantages reduce the error vector magnitude (EVM) degradation at the extended back-off operating point.

The fundamental design parameter defining asymmetry. In an asymmetric Doherty, the peaking amplifier's transistor periphery is larger than the carrier's, typically with ratios of 1.5:1 or 2:1. This increases the peaking device's saturated power capability, allowing it to supply more current during load modulation. The higher current injection shifts the efficiency peak to a deeper back-off point—often 8-10 dB—matching modern signals with high PAPR. The ratio directly determines the back-off level where maximum efficiency occurs.

The primary motivation for asymmetric design. While a symmetric Doherty achieves peak efficiency at 6 dB OBO, an asymmetric configuration pushes this to 8-12 dB or more. This is critical for 5G and Wi-Fi signals with PAPR exceeding 10 dB. The extended range means the amplifier operates closer to peak efficiency during average power transmission, dramatically reducing base station energy consumption and thermal load. The back-off extension is proportional to the peaking-to-carrier power ratio.

To achieve proper load modulation with mismatched devices, the input signal must be split unequally. An asymmetric power divider or coupler directs more RF drive to the larger peaking amplifier and less to the carrier. This compensates for the different gain characteristics of the two paths and ensures the peaking device turns on at the correct threshold. Without proper uneven drive, the efficiency enhancement and linearity of the asymmetric Doherty are severely compromised.

Asymmetric devices introduce unequal phase delays in the carrier and peaking paths due to different input capacitances and matching networks. Dedicated phase offset lines must be inserted to realign the signals at the combiner input. Without precise phase alignment, the power combining is destructive rather than constructive, collapsing efficiency and output power. This becomes more challenging at wider bandwidths where phase dispersion across frequency must be managed.

Asymmetric Doherty amplifiers exhibit more complex nonlinear behavior than symmetric designs. The uneven turn-on characteristics and different compression profiles of mismatched devices create stronger AM-PM distortion and more pronounced memory effects. The DPD model must capture the composite nonlinearity of two dissimilar transistors operating in different classes. Generalized memory polynomial or neural network models are often required, increasing the coefficient count and adaptation complexity compared to symmetric DPD.

Asymmetric designs inherently have lower overall gain than symmetric counterparts because the larger peaking device, biased in deep Class-C, provides less gain. The composite gain also exhibits a non-monotonic profile—gain expansion can occur as the peaking amplifier activates. This gain variation must be carefully managed through driver stage design and is a key input to the DPD algorithm. The expanded gain region can actually aid linearization if properly characterized in the behavioral model.