RTOS Scheduling

An RTOS kernel always runs the highest-priority ready task. If a high-priority task (e.g., a burst detector interrupt) becomes ready, it immediately preempts a lower-priority task (e.g., a logging routine). This ensures that time-critical classification jobs are never blocked by background activities. Priority assignment is a critical design step, often using Rate Monotonic Analysis (RMA) for periodic tasks.

The time from a hardware interrupt (e.g., ADC buffer full) to the execution of the first instruction of the Interrupt Service Routine (ISR) is bounded and constant. Unlike general-purpose OSes, an RTOS minimizes critical sections where interrupts are disabled. This guarantees that the system can react to a new signal burst within a known, fixed number of microseconds, preventing sample loss.

RTOS applications typically operate from a single, statically allocated memory map. Dynamic memory allocation (malloc) is avoided in critical paths to prevent non-deterministic fragmentation and latency spikes. Crucially, virtual memory paging to disk is disabled, as a page fault would introduce an unpredictable delay of milliseconds, violating the real-time inference budget.

Tasks share data (e.g., IQ sample buffers) using mutexes and semaphores. A classic pitfall is priority inversion, where a high-priority task waits for a mutex held by a low-priority task. RTOSes prevent this using mechanisms like the priority inheritance protocol, which temporarily elevates the low-priority task's priority to allow it to release the resource quickly, bounding the blocking time.

For deployed edge sensors, an RTOS can enter a low-power state between signal bursts. A tickless kernel disables the periodic system tick interrupt when the system is idle, allowing the processor to sleep deeply until woken by an external event (e.g., a signal crossing a threshold). This dramatically extends battery life without compromising the deterministic wake-up latency required for capture.

In safety-critical systems, an RTOS can enforce spatial and temporal partitioning. This means a classification task is guaranteed a fixed time window and memory budget, regardless of what other tasks are doing. If a lower-criticality task hangs or overruns, the RTOS's health monitoring can terminate it without affecting the core signal processing pipeline, ensuring the classifier continues to meet its deadlines.

A hard real-time constraint ensuring the time from signal reception to classification output is constant and predictable. In RTOS scheduling, this is achieved through priority-based preemption where the inference task is guaranteed CPU cycles within a fixed deadline. For electronic warfare systems, missing a deadline is considered a system failure, not just a performance degradation.

• Jitter must be bounded to microseconds
• Achieved via priority ceiling protocols
• Critical for time-sensitive SIGINT operations

A classic RTOS pitfall where a high-priority inference task is blocked by a low-priority task holding a shared resource. This can cause missed classification deadlines. Mitigation strategies include the priority inheritance protocol, where the blocking task temporarily inherits the priority of the blocked task.

• Common in mutex-locked DSP buffers
• Priority ceiling protocol prevents deadlocks
• Must be analyzed during worst-case execution time (WCET) profiling

The RTOS kernel's ability to forcibly suspend a running task to execute a higher-priority one. For modulation classification, this means an IQ sample processing task can be interrupted by a burst detection ISR that triggers immediate capture. Unlike cooperative multitasking, preemption guarantees that the highest-priority ready task always runs.

• Context switch time is a critical performance metric
• Typically under 1 microsecond on ARM Cortex-M7
• Enforces strict priority ordering at all times

A static priority assignment algorithm where tasks with shorter periods receive higher priorities. In an SDR pipeline, a 100 µs IQ streaming task gets higher priority than a 1 ms classification task. This is provably optimal for fixed-priority preemptive scheduling when task deadlines equal their periods.

• Assumes periodic, independent tasks
• CPU utilization bound is approximately 69%
• Forms the theoretical basis for many RTOS configurations

A hardware-triggered function that executes immediately when an RF event occurs, such as a DMA transfer complete or ADC buffer full. ISRs must be extremely short to avoid blocking other interrupts. Best practice is to defer processing to a deferred procedure call (DPC) or high-priority task.

• Runs in interrupt context, not task context
• Cannot block or take mutexes
• Signals a semaphore to wake the processing task