IQ Streaming Pipeline

The pipeline must guarantee a constant, predictable time from signal reception to classification output. Unlike best-effort networks, a deterministic system ensures that the inference latency budget is never exceeded, which is critical for time-sensitive electronic warfare and dynamic spectrum access. This requires RTOS scheduling and pre-allocated resources to avoid garbage collection pauses or OS jitter.

To minimize CPU overhead and memory bandwidth utilization, data is transferred between processing stages by passing pointers rather than physically copying the IQ samples. A circular buffer structure manages the infinite stream of samples within a finite memory footprint, overwriting the oldest data first. This technique is essential for bare-metal inference and high-throughput FPGA offload scenarios.

Raw RF samples are rarely fed directly to a neural network. The pipeline integrates hardware-accelerated preprocessing blocks, typically on an FPGA, to perform:

• Digital Down Conversion (DDC) to translate signals to baseband
• Sample rate decimation to match the classifier's input requirements
• Polyphase filter banks for wideband channelization This offloads the general-purpose CPU and reduces the data volume before inference.

A robust streaming pipeline implements backpressure handling to prevent data loss when a downstream stage is saturated. If the inference engine cannot keep up with the incoming sample rate, it signals upstream producers to throttle acquisition. This is often implemented using gRPC streaming or shared memory semaphores, ensuring graceful degradation rather than catastrophic buffer overflows.

Continuous classification of noise is computationally wasteful. The pipeline employs burst detection algorithms, such as CFAR (Constant False Alarm Rate), to dynamically identify the start of a transient signal transmission. Only upon detection is a coherent sample buffer captured and dispatched to the classifier, dramatically reducing the average inference duty cycle and power consumption on edge hardware.

Coherent signal processing requires a globally synchronized clock. A GPS-disciplined oscillator (GPSDO) provides a highly accurate 10 MHz reference and 1 PPS signal, enabling precise timestamping of IQ samples. This is fundamental for VITA 49 packetized transport over IP networks and for correlating signals across distributed sensor nodes in a hardware-in-the-loop test environment.

A technique that digitizes the radio frequency signal directly at the antenna without analog down-conversion. This pushes the digital boundary closer to the signal source, eliminating mixer stages and their associated noise and non-linearity. The resulting raw data stream requires a high-performance IQ streaming pipeline to handle the massive sample rates, often exceeding multiple gigasamples per second.

A memory management technique where data is transferred between processing stages by passing pointers rather than physically copying the data. In an IQ streaming pipeline, this minimizes CPU overhead and latency by avoiding expensive memcpy operations. Implementations often use shared memory regions or DMA transfers between an FPGA and a host processor to move IQ samples directly into the inference engine's address space.

A fixed-size data structure that overwrites the oldest data first, used to manage a continuous, infinite stream of IQ samples within a finite memory footprint. This is essential for capturing a pre-trigger window of samples when a burst detector fires. The buffer acts as a sliding window, ensuring the classifier always receives the most recent N samples without dynamic memory allocation.

The process of identifying the start and end of a transient signal transmission within a continuous stream of noise. A CFAR (Constant False Alarm Rate) algorithm dynamically sets a detection threshold based on the local noise floor. Upon detection, it triggers the capture of a fixed-length sample buffer from the circular buffer, which is then passed to the modulation classifier.

A concurrency model where different stages of the signal processing and inference pipeline run simultaneously on separate compute units. For example, a CPU core handles DDC and decimation while an FPGA or GPU executes the neural network forward pass. This maximizes overall system throughput by ensuring that no stage idles while waiting for the next buffer of data.