Deterministic Latency

The maximum allowable time—typically in microseconds or milliseconds—allocated for a neural network to perform a single forward pass and return a modulation classification result. This budget is a hard constraint derived from the system's overall timing requirements. Exceeding it means the classification is stale and potentially useless for time-sensitive actions like reactive jamming or dynamic spectrum access. The budget directly dictates model complexity, hardware selection, and preprocessing depth.

The use of a Real-Time Operating System to deterministically prioritize and manage DSP and inference tasks. Unlike general-purpose OS schedulers that aim for fairness, an RTOS guarantees that the highest-priority task—such as a modulation classifier—executes within a predefined deadline. It employs preemptive, priority-based scheduling to ensure that a classification cycle is never delayed by a lower-priority background task, making jitter predictable and bounded.

The execution of a compiled neural network directly on a processor without an underlying operating system. By eliminating OS overhead—context switches, system calls, and driver latency—bare-metal inference achieves the lowest possible and most predictable latency. The model is often compiled into a single, monolithic binary using tools like TensorFlow Lite Micro and deployed on a microcontroller or FPGA soft-core, giving the developer absolute control over every CPU cycle.

A concurrency model where different stages of the signal processing and inference pipeline run simultaneously on separate compute units. For example, an FPGA handles FFT and channelization while a dedicated AI accelerator runs the classifier on the previous batch. This maximizes overall system throughput without reducing the latency of a single inference. The key challenge is managing synchronization and backpressure between stages to maintain deterministic end-to-end timing.

A flow control mechanism that prevents data loss when a downstream processing stage is saturated. If the inference engine cannot keep up with the incoming IQ sample rate, backpressure signals upstream producers to throttle or buffer data. In a deterministic system, uncontrolled backpressure is a failure mode; it must be managed through bounded buffers and priority inversion avoidance to ensure that critical classification results are never dropped due to queue overflow.

A memory management technique where data is transferred between processing stages by passing pointers rather than physically copying the data. In a real-time IQ pipeline, the ADC writes samples to a shared memory region, and the classifier reads directly from that same region. This eliminates the memcpy() overhead that would otherwise consume precious microseconds of the latency budget and introduce non-deterministic jitter from cache pollution.