CORDIC Algorithm

CORDIC replaces complex multiplications with simple binary shifts and additions. Each iteration rotates a vector by a decreasing angle stored in a lookup table, converging to the target angle with 1-bit precision gain per step. This eliminates the need for dedicated DSP slices, dramatically reducing FPGA resource utilization.

• Micro-rotation: Each step applies a rotation of arctan(2⁻ⁱ)
• Gain factor: A fixed scaling constant (≈1.64676) compensates for magnitude growth
• Convergence range: ±99.7° for the standard circular mode

CORDIC operates in two fundamental modes, enabling a single hardware block to compute multiple transcendental functions by simply changing the input configuration and interpreting the output differently.

• Rotation Mode: Drives the angle accumulator to zero. Computes sine, cosine, and vector rotation simultaneously from a given angle input
• Vectoring Mode: Drives the Y component to zero. Computes arctangent and vector magnitude (hypotenuse) from given X,Y coordinates
• Unified hardware: The same datapath serves as an NCO, digital mixer, and Cartesian-to-polar converter

For real-time streaming applications like digital down-conversion, CORDIC is implemented as a deeply pipelined systolic array. Each iteration occupies one pipeline stage with dedicated registers, producing a new output sample on every clock cycle after the initial latency.

• Throughput: One result per clock cycle after pipeline fill
• Latency: Equal to the number of iterations (e.g., 16 clocks for 16-bit precision)
• Resource trade-off: Pipelining maximizes throughput at the cost of register usage, ideal for continuous IQ stream processing

A Numerically Controlled Oscillator (NCO) built with CORDIC in rotation mode generates quadrature local oscillator signals (cos θ, sin θ) with exceptional spurious-free dynamic range (SFDR). This is the foundational block for digital down-converters (DDCs) in software-defined radio.

• Phase accumulator: A simple counter drives the CORDIC angle input
• Frequency resolution: Determined by the accumulator bit width and clock rate
• Quadrature output: Simultaneous sine and cosine eliminate the need for separate LUTs or phase-shift networks
• SFDR advantage: CORDIC-based NCOs achieve >100 dB SFDR with sufficient bit width, outperforming direct LUT approaches

Beyond sine and cosine, the CORDIC algorithm generalizes to hyperbolic and linear coordinate systems by changing the micro-rotation angle sequence. This unified approach computes a wide range of functions critical for signal processing and synchronization.

• Hyperbolic mode: Computes sinh, cosh, tanh, eˣ, and ln(x) for exponential scaling and log-likelihood ratios
• Linear mode: Performs multiplication and division directly, useful for gain normalization
• Square root: Derived from hyperbolic vectoring mode, essential for magnitude computation in automatic gain control (AGC) loops

When throughput demands are lower, CORDIC can be folded into a bit-serial or iterative architecture that reuses a single micro-rotation stage, dramatically reducing logic area for cost-sensitive or low-power applications.

• Iterative CORDIC: One stage loops N times, trading throughput for area
• Bit-serial arithmetic: Processes one bit per clock, minimizing interconnect and routing congestion
• Application fit: Ideal for control loops, calibration routines, and slow telemetry processing where a few hundred clock cycles per result is acceptable

A digital circuit that performs frequency translation and sample rate reduction to convert a digitized IF signal to complex baseband. The DDC relies on a Numerically Controlled Oscillator (NCO)—often implemented using CORDIC—to generate the precise sine and cosine values required for quadrature mixing. The architecture typically includes a mixer stage, a CIC decimation filter, and multiple FIR compensation filters to prevent aliasing while preserving the modulated signal's phase and amplitude characteristics.

A digital signal generator that produces a programmable, phase-continuous sinusoidal waveform. The NCO consists of a phase accumulator and a phase-to-amplitude converter. The phase accumulator increments by a tuning word on each clock cycle, and the resulting phase value is converted to a sine/cosine pair. CORDIC in rotation mode is the preferred implementation for the phase-to-amplitude stage in FPGAs because it requires only shift-and-add operations, avoiding the need for large lookup tables or dedicated multiplier blocks.

A computationally efficient structure for channelizing a wideband input signal into multiple narrowband sub-channels. It combines a prototype low-pass filter with a DFT operation implemented via an FFT. The polyphase decomposition reduces the per-channel computation by a factor equal to the number of channels. When paired with a CORDIC-based NCO for fine-frequency tuning, this architecture enables parallel modulation classification across many simultaneous signals without redundant filtering operations.

A complete waveform generation system that integrates an NCO, a digital-to-analog converter (DAC), and a reconstruction filter. The DDS produces agile, high-resolution analog signals with sub-Hertz frequency tuning and instantaneous phase-continuous switching. In test and measurement applications, a DDS using a CORDIC core can generate complex modulated waveforms—including QPSK, QAM, and FSK—by directly computing the required I and Q samples in real time without pre-computed waveform tables.

The CORDIC algorithm itself operates in three distinct modes: rotation mode (computes sine and cosine of a given angle), vectoring mode (computes magnitude and arctangent of a vector), and linear mode (performs multiplication and division). Each iteration uses a fixed set of arctangent constants and performs a conditional addition or subtraction based on the sign of the remaining angle or y-coordinate. The algorithm converges at approximately 1 bit of accuracy per iteration, making it inherently scalable for different precision requirements.

A concurrency architecture where the signal processing chain—DDC, channelizer, feature extractor, and neural network inference—is decomposed into discrete stages that execute simultaneously on separate hardware resources. Each stage processes a different sample block in an assembly-line fashion. CORDIC-based NCOs and FFT butterflies are inherently feed-forward structures that map naturally to deep pipelines, enabling sustained throughput of multiple giga-samples per second on modern FPGAs without backpressure stalls.