Vitis AI

The DPU is a programmable engine optimized specifically for convolutional neural network inference. It features a custom instruction set and a dedicated systolic array to maximize the efficiency of matrix multiplications. Vitis AI configures the DPU's architecture—including the number of Multiply-Accumulate (MAC) units and memory bandwidth—to match the specific needs of your model, enabling high-throughput, low-power execution on adaptive SoCs.

The AI Optimizer employs advanced model compression techniques to reduce the computational footprint of neural networks for edge deployment. It performs iterative weight pruning to remove redundant connections, guided by principles similar to the Lottery Ticket Hypothesis. This is combined with channel pruning to structurally reduce model size, drastically lowering FLOPs Reduction requirements while preserving the accuracy of modulation classification models.

The AI Quantizer converts floating-point models to fixed-point for integer-only inference. It supports Post-Training Quantization (PTQ) with a fast calibration dataset and Quantization-Aware Training (QAT) using a Straight-Through Estimator (STE) for maximum accuracy. A key feature is mixed-precision quantization, which assigns different bit-widths to layers, balancing the trade-off between model size and signal classification fidelity.

The AI Compiler maps the optimized model graph to the DPU's instruction set. It performs critical optimizations including operator fusion, which combines consecutive operations like convolution, bias, and activation into a single kernel. It also executes batch normalization folding, mathematically absorbing BN parameters into preceding weights to eliminate redundant runtime calculations and reduce memory bandwidth bottlenecks.

This tool provides deep visibility into the execution of a model on the DPU. It generates a roof-line model analysis to identify if your workload is memory-bound or compute-bound. The profiler visualizes the streaming architecture dataflow, helping you optimize a ping-pong buffer strategy to overlap data transfer with computation, ensuring continuous, low-latency IQ sample processing for real-time classification.

The Vitis AI Library offers pre-optimized C++ and Python APIs for common tasks like classification, detection, and segmentation, abstracting away low-level DPU programming. The Model Zoo provides a curated collection of pre-trained models, including those suitable for RF tasks, which have been pruned and quantized for optimal performance. This accelerates the deployment of hardware-aware NAS results directly onto Xilinx platforms.

The programmable hardware engine at the heart of Vitis AI, optimized specifically for convolutional neural network inference. The DPU features a custom instruction set and a dedicated systolic array to maximize the efficiency of multiply-accumulate operations. Vitis AI compiles and maps neural network graphs directly onto this IP core, enabling high-throughput, low-latency modulation classification on Zynq and Versal devices.

A critical Vitis AI optimization that reduces the numerical precision of a pre-trained model's weights and activations from 32-bit floating-point to 8-bit integer (INT8) without retraining. The Vitis AI quantizer analyzes the dynamic range of each tensor and applies a calibration dataset to minimize accuracy loss. This is the fastest path to deploying a modulation classifier on a DPU with a 4x reduction in memory footprint.

A technique that simulates the effects of low-precision arithmetic during the forward and backward passes of model training. By inserting fake quantization nodes, the network learns to adapt its weight distribution to compensate for quantization error. Vitis AI supports QAT for modulation classifiers that suffer unacceptable accuracy degradation with standard PTQ, ensuring high performance on INT8 hardware.

A graph-level optimization within the Vitis AI compiler that combines multiple consecutive neural network operations into a single computational kernel. For example, a convolution, batch normalization, and ReLU activation can be fused into one DPU instruction. This eliminates redundant memory bandwidth bottlenecks and kernel launch overhead, significantly reducing latency for real-time IQ sample processing.

A pre-deployment optimization that mathematically absorbs the parameters of a batch normalization layer into the preceding convolutional layer's weights and biases. Since batch norm is a linear operation during inference, this folding eliminates redundant runtime calculations without any loss of mathematical precision. Vitis AI performs this automatically, simplifying the graph before DPU compilation.

An automated design process that translates algorithmic descriptions written in C or C++ into hardware description language for FPGA implementation. Vitis AI leverages HLS to generate custom pre-processing and post-processing kernels that surround the DPU, such as IQ sample normalization or softmax output layers. This accelerates the deployment of complete RF inference pipelines without manual RTL design.