Streaming Architecture

A spatial computing paradigm where the entire signal processing chain is decomposed into discrete, concurrently executing stages. Each clock cycle advances data one stage forward, enabling initiation intervals of 1 and throughput of one sample per clock. For modulation classifiers, this means a new IQ sample enters the FFT or filter stage while previous samples simultaneously occupy the neural network inference layers downstream. The pipeline depth determines end-to-end latency, measured in clock cycles from ADC sample to classification decision, while the initiation interval governs maximum throughput.

A flow control mechanism that prevents data loss when downstream processing stages cannot accept new input. Using AXI4-Stream TREADY/TVALID handshaking, upstream modules stall automatically when a consumer asserts backpressure. In modulation classification pipelines, this occurs when a complex neural network layer requires multiple cycles to compute a result. The architecture propagates stall signals backward through the entire pipeline, ensuring no FIFO overflow and maintaining deterministic data integrity without requiring software intervention or dynamic scheduling.

A directed acyclic graph representation where nodes are computational kernels and edges are streaming FIFO channels. Tools like Vitis HLS and hls4ml automatically synthesize these graphs from C++ or Python descriptions. For RF inference, a typical graph includes:

• Preprocessing: DC offset correction, IQ imbalance compensation
• Feature Extraction: FFT, cyclostationary analysis
• Neural Network: Convolutional layers, activation functions
• Decision Logic: Argmax, confidence thresholding Each node executes independently, enabling task-level parallelism across the entire modulation recognition chain.

A double-buffering technique using two memory banks that alternate between write and read roles. While one buffer accumulates incoming IQ samples, the other feeds previously collected data to the processing pipeline. This decouples data acquisition from computation, allowing the FPGA to overlap DMA transfers from the ADC with neural network inference. For streaming modulation classifiers, ping-pong buffers eliminate the throughput gap between bursty input and continuous processing, ensuring the pipeline never stalls waiting for data. The technique is essential when interfacing with JESD204B high-speed converter interfaces.

A graph-level optimization that merges consecutive operations into a single hardware kernel to eliminate intermediate memory transactions. In streaming modulation classifiers, common fusions include:

• Conv2D + BatchNorm + ReLU: Folding normalization parameters into convolution weights
• MaxPool + Activation: Combining pooling and non-linearity in one pass
• Dense + Softmax: Computing class probabilities without storing the raw logits Fusion reduces off-chip DRAM bandwidth and minimizes pipeline bubbles, directly improving the frames-per-second throughput of real-time signal classification systems.

Unlike GPU or CPU architectures where cache misses and thread scheduling introduce jitter, FPGA streaming pipelines guarantee cycle-accurate, fixed latency from input to output. Every IQ sample traverses exactly the same number of pipeline registers and logic stages. For time-critical applications like electronic warfare or dynamic spectrum access, this determinism enables precise time-of-arrival estimation and synchronous decision-making. The total latency equals the sum of all pipeline stage latencies, computable at compile time through static timing analysis.

A double-buffering memory technique that uses two independent memory banks to decouple the data producer from the data consumer. While one buffer is being filled with incoming IQ samples via DMA, the other is being read by the classifier pipeline. This allows the FPGA accelerator to overlap data transfer with computation, eliminating idle cycles and ensuring continuous streaming inference without backpressure on the ADC interface.

A graph-level optimization that combines multiple consecutive neural network operations into a single computational kernel. For streaming architectures, fusing a convolutional layer with its subsequent batch normalization and activation function eliminates the need to write intermediate tensors to off-chip DRAM. This reduces memory bandwidth bottlenecks and minimizes kernel launch overhead, keeping the entire computation resident in the FPGA's on-chip BRAM and DSP slices.

A homogeneous network of tightly coupled processing elements (PEs) arranged in a grid that rhythmically compute and pass data to neighbors. Each PE performs a multiply-accumulate operation and forwards partial sums. This architecture maps directly to the matrix multiplications central to deep learning, providing a highly efficient hardware template for streaming classifiers where data flows in a deterministic, pipelined fashion without random memory access patterns.

A hardware optimization that concatenates multiple low-precision data elements into a single wide memory word. For a post-training quantized classifier using INT8 weights, four 8-bit values can be packed into a 32-bit bus. This maximizes the utilization of memory bandwidth and SIMD vector units on the target accelerator, allowing the streaming pipeline to process multiple samples per clock cycle without increasing DRAM access frequency.

The fundamental arithmetic operation in digital signal processing and neural network inference, consisting of a multiplication followed by an addition. In FPGA fabric, a single MAC maps directly to a DSP48 slice, which contains a pre-adder, multiplier, and accumulator. The throughput of a streaming modulation classifier is ultimately bounded by the number of available DSP slices and how efficiently they are arranged in a deep pipeline to sustain one MAC per clock cycle.

A visual performance model that plots computational throughput against operational intensity to identify whether a specific neural network workload on a given FPGA is limited by memory bandwidth or compute capacity. For streaming architectures, the goal is to push the operating point above the ridge point into the compute-bound region, where the pipeline is saturating DSP slices rather than stalling on data fetches from external memory.