In-Memory Computing

A two-dimensional grid where memristors at each intersection store conductance values representing weight matrices. When input voltages are applied to rows, the resulting currents along columns physically compute the dot-product via Kirchhoff's current law.

• Analog MVM: Matrix-vector multiplication occurs in O(1) time complexity regardless of matrix dimensions
• Non-volatile storage: Weights persist without power, eliminating data movement between memory and compute units
• Sneak path mitigation: Requires selector devices or complementary resistive switches to prevent unintended current paths

Traditional architectures shuttle data between separate memory and processor units, incurring latency and energy penalties that dominate AI workloads. In-memory computing collapses this distinction.

• Compute where data resides: Arithmetic is performed directly on stored values using analog circuit physics
• Bandwidth wall bypass: Eliminates the memory bus as the primary throughput limiter for data-intensive operations
• Locality maximization: Weight stationary dataflow keeps model parameters fixed in place while activations flow through

Two distinct approaches exist for performing computation within memory arrays, each with different precision and reliability trade-offs for RF inference workloads.

• Analog IMC (AIMC): Uses continuous conductance states and physical laws; susceptible to noise, variability, and ADC/DAC overhead but offers extreme density
• Digital IMC (DIMC): Performs bit-wise logic within modified SRAM cells; deterministic and precise but lower density than analog approaches
• Hybrid approaches: Combine analog dot-product engines with digital accumulation and activation functions for balanced precision-efficiency

The physical memory element determines the fidelity, endurance, and scalability of in-memory computing. Emerging resistive memories provide multi-level conductance states essential for weight encoding.

• RRAM (Resistive RAM): Metal-oxide stacks switch resistance via filament formation; high endurance and CMOS compatibility
• PCM (Phase-Change Memory): Chalcogenide glass transitions between amorphous and crystalline states; mature technology with good multi-level capability
• MRAM (Magnetic RAM): Spin-transfer torque switches magnetic tunnel junctions; infinite endurance but limited resistance ratio
• FeFET (Ferroelectric FET): Uses polarization states for non-volatile threshold voltage shifts; promising for high-density 3D integration

The memory array alone cannot function as a compute engine. Peripheral circuits including DACs, ADCs, and transimpedance amplifiers critically determine overall system performance.

• DAC resolution: Input digital-to-analog converters set the precision of applied voltages; typically 1-4 bits for energy efficiency
• ADC bottleneck: Analog-to-digital conversion of column currents dominates latency and energy; flash ADCs and successive approximation offer different trade-offs
• Transimpedance amplifiers: Convert accumulated currents to voltages with gain; must handle wide dynamic range from large dot-product sums
• Shift-and-add logic: Handles multi-bit weight and activation decomposition for bit-serial computation schemes

Deploying trained models onto in-memory computing hardware requires weight-to-conductance mapping and handling of negative values, large layers, and non-idealities.

• Differential pairs: Each weight is represented by the conductance difference between two memristors to encode both positive and negative values
• Layer tiling: Large weight matrices exceeding crossbar dimensions are partitioned across multiple physical arrays with partial sum accumulation
• Conductance programming: Iterative write-verify algorithms tune each memristor to its target conductance within acceptable error tolerance
• Batch normalization folding: BN parameters are mathematically absorbed into weights and biases before mapping to avoid runtime analog division