High-Level Synthesis (HLS)

HLS compiles untimed algorithmic descriptions written in C++ directly into synthesizable Register-Transfer Level (RTL) code. This eliminates the need for engineers to manually describe finite state machines and data paths in Verilog or VHDL, collapsing months of hardware design into days of software-like iteration. The tool automatically schedules operations across clock cycles, infers memory architectures, and binds functional units to hardware resources based on user-defined constraints.

Hardware micro-architecture is controlled through compiler directives rather than code rewrites. Key pragmas include:

• PIPELINE: Overlaps loop iterations to achieve initiation intervals of 1
• UNROLL: Replicates loop bodies for parallel execution
• ARRAY_PARTITION: Splits BRAM into multiple banks for simultaneous access
• DATAFLOW: Enables task-level pipelining between sequential functions This allows rapid design space exploration without altering algorithmic correctness.

HLS natively supports hls::stream and ap_axis interfaces that model infinite FIFO channels. For RF inference, this maps directly to the continuous arrival of IQ samples from an ADC. The compiler synthesizes deep pipelines where each stage processes a sample per clock cycle, achieving deterministic ultra-low latency—often sub-microsecond—by eliminating the need for frame-based batch processing common in GPU inference.

Unlike CPUs and GPUs constrained to 8/16/32/64-bit boundaries, HLS allows arbitrary precision integers and fixed-point types (e.g., ap_int<7>, ap_fixed<12,4>). This is critical for deploying quantized neural networks where weights and activations may use non-standard bit-widths like 3-bit or 6-bit. The compiler synthesizes exactly the required logic, eliminating wasted silicon and reducing dynamic power consumption proportionally to the bit-width reduction.

The HLS compiler automatically infers multiply-accumulate (MAC) operations and maps them to dedicated DSP48 slices in Xilinx FPGAs. A single DSP48 can perform a P = A * B + C operation in one clock cycle. For neural network inference, the tool can pack multiple low-precision multiplications into a single DSP48 using techniques like INT8 dot-product mode, effectively doubling or quadrupling the computational throughput of the fabric without increasing resource utilization.

HLS tools include automated co-simulation frameworks that verify the generated RTL against the original C++ testbench. The same test vectors drive both the algorithmic model and the cycle-accurate hardware simulation, with automatic assertion checking on the outputs. This eliminates the classic hardware-software verification gap and ensures that the synthesized modulation classifier produces bit-identical results to the floating-point reference model used during training.

An FPGA dataflow design pattern where data is processed as a continuous sequence of samples using deep pipelines. This achieves minimal processing latency for real-time IQ sample classification by eliminating external memory round-trips.

• Uses hls::stream for FIFO-based inter-module communication
• Enables line-rate processing at ADC sample speeds
• Critical for electronic warfare and tactical SIGINT applications

The fundamental Multiply-Accumulate (MAC) computational primitive in Xilinx FPGA fabric. HLS tools automatically map multiplication and addition operations onto these hardened blocks.

• Each DSP48E2 supports 27×18-bit multiplication
• Critical resource for implementing convolutional layers in modulation classifiers
• HLS RESOURCE directives control DSP vs. LUT mapping trade-offs

A hardware optimization that concatenates multiple low-precision data elements into a single wide memory word. This maximizes memory bandwidth utilization and SIMD vector unit efficiency on the target accelerator.

• Packs 8× 4-bit weights into a single 32-bit word
• Reduces external memory access count proportionally
• Implemented via HLS struct packing and ap_uint types

A double-buffering memory technique that uses two banks to decouple the data producer and consumer. This allows the FPGA accelerator to overlap data transfer with computation for continuous streaming inference.

• Eliminates pipeline stalls during DMA transfers
• Essential for maintaining real-time throughput in RF classifiers
• Implemented with #pragma HLS DATAFLOW and dual-port BRAM