Hardware-Aware NAS

The foundational automated methodology that hardware-aware NAS extends. NAS uses search strategies like reinforcement learning, evolutionary algorithms, or gradient-based methods to explore the design space of neural network topologies. Instead of manual trial-and-error, a NAS controller samples architectures—varying layer types, kernel sizes, and channel counts—and evaluates their performance on a proxy task. The search objective traditionally maximizes validation accuracy, but hardware-aware variants add latency, energy, or memory constraints to the reward function.

A pre-built database that maps individual neural network operations to their measured execution times on a specific FPGA target. During hardware-aware NAS, the search algorithm queries this table to estimate the end-to-end inference latency of a candidate architecture without performing full synthesis and place-and-route for every candidate. This decouples architecture evaluation from the slow hardware compilation loop, accelerating the search by orders of magnitude. Lookup tables typically profile convolution, depthwise convolution, and fully-connected layers across varying input shapes and channel dimensions.

A candidate neural network design where no other architecture in the search space simultaneously achieves better accuracy and better hardware efficiency. The Pareto frontier represents the set of non-dominated solutions, allowing engineers to select the optimal trade-off for their deployment scenario. For modulation classification on FPGAs, a Pareto-optimal model might balance classification accuracy against inference latency in microseconds or energy per inference in millijoules, providing a menu of deployable options rather than a single point solution.

A gradient-based NAS method that relaxes the discrete architecture search space into a continuous one, enabling optimization via stochastic gradient descent. DARTS assigns a learnable mixing weight to each candidate operation between every pair of nodes in a supergraph. Hardware-aware extensions, such as Hardware-Aware DARTS, incorporate a differentiable latency term into the loss function, allowing the search to jointly optimize for accuracy and hardware cost in a single end-to-end training loop. This dramatically reduces the search cost compared to black-box methods.

A progressive shrinking approach that trains a single large supernet supporting diverse sub-architectures through weight sharing. The supernet is trained once to simultaneously support elastic depth, width, kernel size, and resolution dimensions. After training, a separate search phase evaluates sub-networks against hardware constraints using an accuracy predictor and a latency lookup table. This decouples training from search, enabling rapid deployment of specialized models for different FPGA targets without retraining. Key for modulation classifiers that must adapt to varying resource budgets.

A population-based optimization approach that evolves a set of neural architectures over generations using genetic operators like crossover and mutation. Each individual in the population represents a candidate architecture, evaluated on multiple conflicting objectives: validation accuracy, FPGA latency, and DSP slice utilization. Non-dominated sorting genetic algorithms (NSGA-II) maintain diversity along the Pareto frontier. This method excels at exploring irregular, non-differentiable search spaces common in hardware-constrained NAS for custom RF pipelines.