Batch Normalization Folding

A graph-level optimization that combines multiple consecutive neural network operations into a single computational kernel. Batch normalization folding is a specific instance of operator fusion where the batch norm parameters are mathematically absorbed into the preceding convolution's weights and biases.

• Eliminates intermediate memory reads and writes between fused layers
• Reduces kernel launch overhead on GPU and FPGA accelerators
• Often combined with activation function fusion (e.g., Conv-BN-ReLU into a single op)
• Critical for achieving real-time inference on streaming IQ sample pipelines

A compression technique that reduces the numerical precision of a pre-trained neural network's weights and activations without requiring retraining. After batch normalization folding removes the BN layer's runtime calculations, PTQ converts the resulting folded weights from FP32 to INT8 or lower bit-widths.

• Enables efficient execution on fixed-point DSP slices within FPGA fabric
• Typical accuracy drop of less than 1% for 8-bit quantization of modulation classifiers
• Requires calibration data to determine optimal clipping ranges for activation tensors
• Works synergistically with folding: fewer distinct layers mean fewer quantization boundaries

A deployment mode where all neural network arithmetic is performed using integer operations, eliminating the need for floating-point units. Batch normalization folding is a prerequisite for pure integer inference because the BN layer's division and square-root operations are incompatible with integer-only execution.

• The folded convolution weights absorb the BN scale, shift, mean, and variance as fixed integer values
• Enables deployment on microcontrollers and FPGAs without hardware FPU support
• Uses the equation: y = (scale * (x - mean) / sqrt(var + epsilon)) + shift folded into W_folded = W * (scale / sqrt(var + epsilon))
• Critical for achieving sub-millisecond latency in real-time spectrum classification

A pre-quantization technique that adjusts the weights across consecutive layers to balance their dynamic ranges. When combined with batch normalization folding, cross-layer equalization exploits the scale parameters absorbed from the BN layer to redistribute weight magnitudes.

• Minimizes the performance degradation caused by per-tensor quantization of activations
• Uses the BN layer's learned scale parameter (gamma) to identify and correct weight imbalance
• Particularly effective for depthwise separable convolutions used in efficient RF classifiers
• Often applied immediately after folding and before the quantization calibration step

An automated design process that translates algorithmic descriptions written in C or C++ into hardware description language for FPGA implementation. When deploying a folded and quantized modulation classifier, HLS tools generate custom dataflow pipelines that exploit the simplified layer structure.

• The elimination of BN layers via folding reduces the number of distinct hardware modules required
• Enables direct mapping of the fused Conv-BN weights to on-chip BRAM and DSP slices
• Tools like Vitis AI and hls4ml automate the conversion of folded TensorFlow or PyTorch models to FPGA bitstreams
• Supports streaming architectures where IQ samples are processed continuously without buffering

The fundamental arithmetic operation in digital signal processing and neural networks, consisting of a multiplication followed by an addition. Batch normalization folding directly reduces the total MAC count required for inference by eliminating the per-channel multiply and add operations of the BN layer.

• A standard BN layer requires 2 MACs per activation: one multiply by scale and one add of shift
• Folding removes these operations entirely, mapping them to the convolution's existing MACs
• For a ResNet-18 classifier processing 1024-sample IQ inputs, folding can save over 500,000 MACs per inference
• Each saved MAC translates directly to reduced energy consumption and lower latency on FPGA DSP48 slices