Log-Likelihood Ratio (LLR)

The absolute value of an LLR quantifies the confidence of the decision. A large positive or negative value indicates high certainty.

• |LLR| ≈ 0: The receiver is completely uncertain; the bit is equally likely to be a 0 or a 1.
• |LLR| → ∞: Absolute certainty. This occurs in the absence of noise or interference.
• Sign: The sign alone provides the hard decision (positive for bit 1, negative for bit 0).

This property allows iterative decoders like Belief Propagation to weight messages appropriately, preventing uncertain bits from corrupting the convergence process.

For statistically independent bits, the combined LLR is simply the sum of the individual LLRs.

• LLR(b₁, b₂) = LLR(b₁) + LLR(b₂)
• This linear property is the mathematical foundation for Factor Graph processing.
• It allows decoders to combine intrinsic channel information with extrinsic information from other decoders without complex probability multiplications.

In MIMO-OFDM systems, this additivity enables the efficient combination of LLRs across different spatial streams and frequency subcarriers before final decoding.

Under Additive White Gaussian Noise (AWGN), the LLR computation simplifies to a linear scaling of the received symbol.

• LLR ∝ (channel_gain / noise_variance) × received_value
• The scaling factor is the Channel State Information (CSI) divided by the noise power.
• This linear relationship is why MMSE and Zero-Forcing receivers can generate LLRs with low computational complexity.

Deviations from this Gaussian assumption, such as non-Gaussian interference or hardware impairments, require more complex LLR computation methods.

A correctly computed LLR satisfies the consistency condition: the sign of the LLR must match the true transmitted bit on average.

• Symmetry: The probability density function of LLRs given bit 0 is the mirror image of the PDF given bit 1.
• LLR = log[ P(y|b=1) / P(y|b=0) ]
• This symmetry ensures that a decoder's decision rule is unbiased.

Violations of this property, often caused by inaccurate Channel Estimation or residual interference after Successive Interference Cancellation, lead to systematic decoding errors.

Exact LLR computation for MIMO requires summing over an exponentially large set of symbol vectors. The Max-Log approximation reduces this to a simple difference of minimum distances.

• LLR ≈ (1/No) × [ min|y - Hs₀|² - min|y - Hs₁|² ]
• This avoids complex exponential and logarithmic operations.
• It is the standard approach for Maximum Likelihood Detection and Sphere Decoding implementations.

While sub-optimal, the performance loss is typically negligible at high SNR and is compensated for by applying a small scaling factor to the extrinsic LLRs.

In iterative Turbo and LDPC decoding, a strict separation between intrinsic and extrinsic information is mandatory.

• A Priori LLR (La): Prior belief about a bit, fed into a decoder from a previous stage.
• Extrinsic LLR (Le): The new, independent information generated by the decoder, computed as the difference between the output a posteriori LLR and the input a priori LLR.
• Le = L_posteriori - La - L_channel

Passing the full a posteriori LLR back would create positive feedback loops and prevent convergence. This subtraction is critical for Successive Interference Cancellation loops in MIMO receivers.

The decoding paradigm that uses Log-Likelihood Ratios as inputs instead of hard binary decisions. Unlike hard-decision decoding which discards reliability information, soft-decision algorithms like the BCJR or Viterbi with soft inputs use the magnitude of the LLR to weigh each bit's contribution. A large positive LLR (+15) indicates high confidence in a '1', while a value near zero (0.1) signals ambiguity. This preserves information from the channel, yielding a typical coding gain of 2-3 dB over hard-decision methods in turbo and LDPC codes.

A computationally efficient algorithm for calculating LLRs in MIMO detection by avoiding complex exponential and logarithmic operations. The standard Log-MAP computes the exact LLR from all possible transmitted vectors, but the Max-Log-MAP simplifies this using the Jacobian logarithm: ln(e^x + e^y) ≈ max(x, y). This reduces complexity by orders of magnitude with only a marginal performance loss of 0.1-0.3 dB, making it the dominant approach in practical soft-output MIMO detectors.

A visualization tool for analyzing the convergence behavior of iterative decoders that exchange LLRs. An EXIT chart plots the mutual information between the transmitted bits and the extrinsic LLRs output by each component decoder. The trajectory through the chart predicts the convergence threshold—the minimum signal-to-noise ratio where the decoder will successfully converge. A tunnel opening between the two transfer curves indicates successful decoding, guiding the design of turbo and LDPC codes.

A detection architecture that accepts a priori LLRs from a channel decoder and produces extrinsic LLRs as output, forming the core of iterative detection and decoding loops. Key algorithms include:

• List Sphere Decoding: Searches a constrained set of candidate vectors to compute LLRs
• Soft MMSE with Parallel Interference Cancellation: Linear filtering with feedback
• Markov Chain Monte Carlo methods: Statistical sampling for LLR approximation This turbo principle exchanges soft information between the MIMO detector and channel decoder, approaching optimal joint detection performance.

A coded modulation architecture where encoding and modulation are separated by a bit-level interleaver, making LLR calculation essential. The interleaver breaks burst errors into isolated bit errors, and the receiver computes LLRs for each coded bit independently from the received symbol. BICM with iterative demapping feeds back extrinsic LLRs from the decoder to refine symbol-level soft information. This is the standard architecture in WiFi (802.11n/ac/ax), LTE, and 5G NR physical layers.

Practical implementation techniques for representing LLRs in fixed-point hardware with limited bit widths. Key considerations:

• Clipping threshold: Saturating extreme LLR values (e.g., ±8) prevents overflow while preserving essential reliability information
• Uniform quantization: Using 4-6 bits per LLR with step sizes of 0.5-1.0 provides near-floating-point performance
• Non-uniform quantization: Allocating more levels near zero where decisions are ambiguous Poor quantization can introduce a 0.5-1.0 dB penalty, making this critical for FPGA and ASIC implementations.