I/Q Pipeline

The pipeline front-end must handle continuous, unbounded I/Q streams from software-defined radios (SDRs) without backpressure or sample loss. This requires a zero-copy ring buffer architecture in shared memory, allowing the radio driver to write samples directly while the preprocessing engine reads asynchronously. Key mechanisms include:

• Lock-free queues to prevent thread contention between producer (radio) and consumer (GPU transfer).
• Circular buffers sized to absorb bursty transfers, typically holding 100-500ms of samples to tolerate scheduling jitter.
• Timestamp alignment using hardware PPS (Pulse Per Second) signals to maintain sample-accurate synchronization across multiple channels.

Raw I/Q samples undergo a fixed sequence of signal conditioning operations compiled into a directed acyclic graph (DAG). Each node in the graph applies a specific transformation—I/Q correction, DC offset removal, normalization, and resampling—with the output feeding the next stage. Determinism is critical: the same input must produce an identical output tensor for reproducible inference. The graph typically includes:

• Gain normalization to scale amplitude to a fixed range (e.g., unit variance) regardless of receiver AGC state.
• Carrier frequency offset (CFO) compensation via digital mixing to center the constellation.
• Sample rate decimation using polyphase filters to match the classifier's native input rate.

The continuous preprocessed stream is partitioned into fixed-length, potentially overlapping segments that form individual inference examples. The segmentation engine applies a sliding window with configurable stride and length, typically 1024 or 2048 complex samples per segment. Each segment then receives a tapering window (Hamming, Blackman, or Kaiser) to minimize spectral leakage if a subsequent FFT-based transformation is used. Critical parameters include:

• Segment duration: Must capture enough symbols for modulation discrimination (e.g., 256+ symbols).
• Overlap factor: 50% overlap is common to avoid missing transient signals at segment boundaries.
• Windowing function: Chosen based on the dynamic range requirements of downstream feature extraction.

Individual I/Q segments are aggregated into batched tensors to maximize GPU utilization during inference. The assembly stage stacks multiple segments along a batch dimension, producing a tensor of shape [batch_size, 2, num_samples] for dual-channel real-valued input or [batch_size, num_samples] for complex-valued input. This stage manages:

• Dynamic batching: Accumulating segments until a target batch size (e.g., 64 or 128) is reached or a latency deadline expires.
• Zero-padding: Handling variable-length segments by padding shorter sequences to a uniform length.
• Memory pinning: Using CUDA-pinned host memory to enable direct memory access (DMA) transfers to the GPU without intermediate copies.

The pipeline's final stage is a low-latency transfer path that moves batched tensors from CPU memory to the inference accelerator. For GPU targets, this uses RDMA (Remote Direct Memory Access) or GPUDirect to bypass the CPU entirely, streaming data directly from the SDR's PCIe interface to GPU memory. For FPGA targets, the pipeline may feed samples directly into a streaming AXI4-Stream interface on the fabric. Key performance metrics:

• Transfer latency: Must be sub-millisecond to maintain real-time classification.
• Throughput: Must sustain the full sample rate without dropping batches.
• Double-buffering: Overlapping the transfer of batch N+1 with the inference of batch N.

A production I/Q pipeline requires comprehensive observability to detect stalls, overflows, and timing violations. Each stage emits metrics—queue depth, processing latency, dropped sample count—to a monitoring backend. A backpressure mechanism propagates downstream congestion upstream: if the GPU inference queue is full, the batching stage slows ingestion, which signals the SDR buffer to throttle. This prevents unbounded memory growth and ensures graceful degradation under load. Common telemetry includes:

• End-to-end latency histogram from antenna to classification output.
• Buffer watermark levels to detect imminent overflows.
• Sample drop counters with timestamps for root-cause analysis.

The critical signal conditioning sequence applied to raw IQ samples to create a standardized input tensor for machine learning classifiers. This pipeline stage includes:

• Normalization: Scaling amplitude to prevent numerical instability
• Centering: Removing residual Carrier Frequency Offset (CFO)
• Filtering: Rejecting out-of-band interference Proper preprocessing ensures the neural network focuses on modulation structure rather than hardware artifacts.

The division of a continuous IQ stream into fixed-length, non-overlapping or overlapping segments to form individual inference examples. Key techniques:

• Sliding windows with 50% overlap for increased temporal resolution
• Hamming or Blackman windows to reduce spectral leakage before FFT transformation
• Segment length directly impacts classification latency vs. accuracy trade-off Typical segment sizes range from 128 to 1024 complex samples per inference frame.

A data regularization technique that applies realistic channel impairments to synthetic or collected IQ samples to expand training dataset diversity. Common augmentations include:

• Phase rotation: Teaching classifiers rotational invariance
• Additive White Gaussian Noise (AWGN): Simulating thermal noise at various SNR levels
• Fading profiles: Applying Rayleigh or Rician multipath models This prevents overfitting and improves generalization to real-world channel conditions.

The process of changing the sample rate of an IQ stream through decimation or interpolation to match the native input requirements of a downstream neural network classifier. Critical considerations:

• Decimation: Reducing sample rate with anti-aliasing filtering to prevent spectral folding
• Interpolation: Increasing sample rate with appropriate reconstruction filters
• Mismatched sample rates cause dimensionality errors in fixed-input neural architectures Rational resampling factors preserve the modulation's spectral signature.

A time-frequency representation generated by applying the Short-Time Fourier Transform (STFT) to an IQ stream, converting raw time-domain samples into a 2D image suitable for Convolutional Neural Networks (CNNs). Pipeline parameters:

• FFT size: Determines frequency resolution
• Hop length: Controls temporal resolution and overlap
• Window function: Minimizes spectral leakage artifacts Spectrograms reveal modulation-specific patterns like frequency hops and chirp rates.

A digital signal processing block that applies inverse filtering to compensate for hardware non-idealities before classification. This pipeline stage addresses:

• I/Q Imbalance: Correcting gain and phase mismatches between I and Q paths
• DC Offset: Removing constant bias from the analog front-end
• Sample Synchronization: Recovering optimal sampling instants to minimize inter-symbol interference Without correction, constellation diagrams appear warped, degrading classification accuracy.