Memory-Augmented Networks

A dedicated, addressable memory bank—typically a matrix M of dimension N × d—that stores vector representations independently from the controller network's internal parameters. Unlike recurrent hidden states, this memory persists across time steps and can be selectively updated.

• Capacity: Fixed-size memory slots (N) each holding a d-dimensional vector
• Persistence: Information remains until explicitly overwritten, preventing catastrophic forgetting
• Example: In a 5-way 1-shot modulation task, the memory can store one support example per class for direct comparison

A neural network—often an LSTM, GRU, or feedforward architecture—that orchestrates interactions with the external memory. The controller emits read heads and write heads that determine what to retrieve and where to store information.

• Input: Concatenation of current input and last read vector
• Output: Parameters for memory access operations (keys, strengths, erase/add vectors)
• Role: Acts as the central processing unit, decoupling computation from storage capacity

A retrieval mechanism where memory locations are accessed by comparing a query key emitted by the controller against all stored vectors using a similarity measure, typically cosine similarity followed by softmax normalization.

• Mechanism: w(i) = softmax(β · cosine_sim(k, M[i]))
• Key strength β: Controls the sharpness of the attention distribution
• Benefit: Enables associative recall—retrieving stored modulation prototypes that are semantically similar to a query signal

Memory updates are performed through a two-step process: an erase vector selectively removes information from a location, followed by an add vector that writes new content. This enables fine-grained, differentiable memory modification.

• Erase: M[i] ← M[i] · (1 − w(i) · e), where e ∈ [0,1]^d
• Add: M[i] ← M[i] + w(i) · a
• Use case: Storing a new modulation signature from a single IQ sample while preserving previously learned classes

A memory management strategy that tracks usage patterns and preferentially overwrites the least recently read locations. This temporal addressing mechanism prevents the memory from saturating with stale information during sequential few-shot tasks.

• Usage vector u: Decays over time, incremented on reads/writes
• Allocation weighting: Combines usage with content-based addressing
• Advantage: Enables the network to autonomously manage limited memory capacity without external garbage collection

The defining capability of memory-augmented networks: encoding a novel class from a single support example and immediately retrieving that representation when a matching query is presented. This mimics the fast-binding property of biological memory systems.

• Encoding latency: Single forward pass to write a new modulation prototype
• Retrieval: Content-based read returns the stored prototype for similarity comparison
• Result: Achieves competitive N-way K-shot accuracy without any fine-tuning or gradient steps on the support set

The core architectural component that differentiates memory-augmented networks from standard neural networks. This is a differentiable key-value store that the controller network can write to and read from via soft attention mechanisms. Unlike the fixed capacity of an LSTM's internal state, the external memory provides stable, long-term storage that persists across many processing steps. For few-shot modulation recognition, the support set is explicitly written into memory slots, allowing the network to retrieve and compare stored signal features when classifying a query sample. Architectures like the Neural Turing Machine (NTM) and Differentiable Neural Computer (DNC) pioneered this approach.

The neural network—typically an LSTM or feed-forward network—that interfaces with the external memory module. The controller performs three critical functions:

• Write Operations: Encodes support set samples into memory slots, often using a key derived from the input features and a value representing the class label or full feature vector.
• Read Operations: Generates a query vector from a test sample and retrieves the most relevant memory contents via cosine similarity or dot-product attention.
• Output Generation: Combines the retrieved memory readout with the query's own features to produce a final classification decision. The controller is trained end-to-end with the memory, learning optimal read/write strategies for rapid assimilation of novel modulation types.

The mechanism by which the controller reads from the external memory. Instead of accessing a discrete address, the controller emits a query key that is compared against all stored memory keys using a similarity function. The resulting attention weights define a soft, differentiable readout that is a weighted sum of memory values. This allows gradient-based optimization of the entire retrieval process. In few-shot modulation classification, this enables the network to:

• Compare a query signal's features against all stored support examples simultaneously.
• Interpolate between similar modulation types when the query falls near a decision boundary.
• Ignore irrelevant memory slots, focusing only on the most similar stored signal templates.

Critical mechanisms for preventing memory corruption and ensuring stable few-shot inference. Without proper management, a controller can overwrite previously stored support set information, degrading classification accuracy. Key strategies include:

• Least Recently Used (LRU) Addressing: The controller learns to write new information to the least recently accessed memory slots, preserving frequently used support set features.
• Temporary Write Gates: A learned gating mechanism that restricts write operations after the support set has been fully encoded, effectively freezing the memory during query processing.
• Separate Read/Write Heads: Architecturally distinct attention heads for reading and writing, preventing interference between retrieval and storage operations. These techniques are essential for maintaining consistent few-shot performance across multiple query batches in streaming modulation recognition scenarios.