Cumulant-Based FPGA Implementation

Implements a recursive, sample-by-sample update of cumulant statistics, eliminating the need for batch processing and large memory buffers. The architecture uses online moment accumulation where each new IQ sample updates running estimates of second, third, and fourth-order moments. This approach achieves deterministic latency independent of observation window length.

• Uses single-pass accumulation registers for raw moments
• Avoids matrix inversions through rank-1 updates
• Maintains constant O(1) memory per cumulant order
• Outputs updated cumulant features every clock cycle after initial convergence

A multi-stage classification architecture that partitions the modulation candidate set using cascaded cumulant thresholds. The first stage separates PSK from QAM using kurtosis, the second stage discriminates sub-Gaussian from super-Gaussian modulations, and subsequent stages refine to specific orders. This coarse-to-fine approach minimizes the number of cumulant orders that must be computed for each decision.

• Stage 1: Gaussianity test separates OFDM from linear modulations
• Stage 2: |C40|/|C42| ratio partitions QAM subsets
• Stage 3: C61 skewness resolves rotationally ambiguous pairs
• Each stage gates downstream computation, saving dynamic power

Multiple cumulant orders (C20, C21, C40, C41, C42, C60, C61, C63) are computed simultaneously in dedicated hardware lanes. Each lane contains independent multiply-accumulate (MAC) units optimized for the specific moment products required. This spatial parallelism exploits the FPGA's fabric to achieve throughput that scales with the number of cumulant orders rather than serializing computation.

• Dedicated DSP48 slices for complex multiply operations
• Pipelined reduction trees for moment summation
• Independent normalization dividers for scale invariance
• All cumulant features available in the same clock cycle

Custom fixed-point number representations are designed for each cumulant order based on its expected dynamic range and required classification accuracy. Higher-order cumulants (C63, C80) require wider bit widths to avoid overflow, while lower-order cumulants can use narrower formats. This heterogeneous precision approach minimizes DSP and BRAM utilization without degrading classification performance.

• C20/C21: 18-bit fixed-point with 12 fractional bits
• C40/C42: 24-bit fixed-point with 16 fractional bits
• C63/C80: 32-bit fixed-point with 20 fractional bits
• Saturation arithmetic prevents wrap-around errors
• Validated against floating-point reference models to ensure < 0.1% feature error

Implements a sliding window architecture that maintains multiple overlapping observation windows simultaneously. As new samples arrive, the oldest samples are subtracted from the running cumulant estimates using decaying accumulation buffers. This enables continuous classification updates at the sample rate while maintaining the statistical reliability of a full observation window.

• Configurable window lengths from 256 to 4096 samples
• 50% overlap between consecutive classification decisions
• Circular buffer with pointer-based sample eviction
• Supports adaptive window sizing based on estimated SNR
• Classification decision updated every N/2 samples for an N-sample window

The cumulant estimation core exposes a standard AXI4-Stream interface for seamless integration with RF data converters and digital down-converters. Raw IQ samples flow directly from ADC interfaces into the cumulant pipeline without CPU intervention. Classification results are output on a separate AXI-Stream port with metadata including confidence scores, estimated SNR, and the cumulant feature vector.

• Input: 16-bit complex IQ samples at sample rate
• Output: Modulation label, confidence, and full cumulant vector
• Backpressure-ready flow control for rate matching
• Compatible with Xilinx RFSoC and ADI ADRV9002 platforms
• Supports multi-channel operation via TDATA field multiplexing

A deeply pipelined hardware architecture that computes higher-order statistics on streaming IQ samples without backpressure. The engine typically interleaves complex multipliers for moment computation with accumulators for time-averaging, achieving one cumulant estimate per clock cycle after initial latency. Key design considerations include fixed-point bit-width propagation to prevent overflow in fourth-power terms and the use of systolic arrays for parallel moment generation across multiple lags.

The process of mapping floating-point cumulant algorithms to fixed-point representations for FPGA efficiency. This involves rigorous dynamic range analysis to determine integer and fractional bit widths that prevent saturation while minimizing quantization error. Techniques include block floating-point scaling, where a shared exponent is maintained for a group of mantissas, and logarithmic number systems for the high-dynamic-range multiplications inherent in fourth-order cumulant computation.

An incremental update scheme that avoids storing the entire sample block for cumulant calculation. Instead of batch processing, the FPGA maintains running estimates of first through fourth-order moments using exponential forgetting factors or sliding window accumulators. This is implemented via circular buffers in Block RAM (BRAM) and recursive difference equations that subtract the oldest sample's contribution while adding the newest, enabling continuous, gap-free modulation monitoring.

A reusable intellectual property block designed using High-Level Synthesis (C/C++ to Verilog/VHDL) to accelerate development. The core encapsulates configurable parameters such as cumulant order (2nd, 4th, 6th), observation length, and normalization mode. Pragmas direct loop unrolling and array partitioning to maximize parallelism, while AXI4-Stream interfaces ensure seamless integration into larger signal processing pipelines within Xilinx Vivado or Intel Quartus environments.

A hardware-efficient method for computing scale-invariant normalized cumulants by replacing costly division operations with pre-computed reciprocal lookup tables stored in distributed RAM. The signal power estimate indexes a dual-port ROM to retrieve the appropriate scaling factor for the fourth-order cumulant. This avoids the multi-cycle latency of divider IP cores and is critical for maintaining the throughput of a streaming classification pipeline where a new normalized feature is required every sample window.

The final classification stage implemented as a combinational logic cascade of comparators that maps cumulant feature values to a modulation label. Theoretical cumulant thresholds for PSK, QAM, and ASK are hard-coded as constants. The FPGA evaluates all branch conditions in parallel using carry-chain logic, producing a classification decision with deterministic, ultra-low latency. This replaces software-based nearest-neighbor or SVM classifiers that are unsuitable for sample-rate processing.