Memory Management Unit (MMU)

The MMU's primary function is to translate virtual addresses generated by software into physical addresses in RAM. This is managed via page tables maintained by the operating system. The MMU uses a Translation Lookaside Buffer (TLB), a dedicated cache, to store recent translations for speed. If a translation is not in the TLB (a TLB miss), the MMU walks the page table in memory to find it.

• Enables Virtual Memory: Allows each process to operate within its own contiguous, isolated address space, regardless of the fragmented physical layout.
• Facilitates Swapping: Permits the OS to move inactive memory pages to disk (swap space) and reload them elsewhere in physical RAM, transparently to the process.

The MMU enforces hardware-level security and stability by controlling which processes can access specific memory regions. Access permissions (read, write, execute) are stored in the page table entries.

• Prevents Illegal Access: Stops a user process from accessing kernel memory or memory belonging to another process, preventing crashes and security exploits.
• Enables Privilege Levels: Supports CPU modes (e.g., user vs. kernel mode) by restricting access to certain memory pages based on the current execution mode.
• W^X Security: Can enforce policies where a page is either Writable or eXecutable, but not both, mitigating certain code injection attacks.

The MMU interacts closely with the CPU's cache hierarchy (L1, L2, L3). It determines the caching properties of memory regions through flags in the page table.

• Cacheability Attributes: Marks memory regions as cacheable or non-cacheable. I/O device memory (via Memory-Mapped I/O) is typically non-cacheable to ensure direct reads/writes.
• Write Policies: Controls whether writes go to cache only (write-back) or to both cache and main memory immediately (write-through).
• Coherency in Multi-Core Systems: Works with cache coherency protocols (e.g., MESI) in Non-Uniform Memory Access (NUMA) systems to ensure all cores have a consistent view of memory.

The MMU generates a page fault exception for the CPU when a requested memory page is not accessible. This triggers the OS to resolve the fault.

• Major Page Fault: The page is not in physical RAM (it's on disk). The OS must load it from the swap file, a slow operation.
• Minor Page Fault: The page is in physical RAM but not mapped in the current process's page table (e.g., a shared library already loaded). The OS simply updates the page table.
• Invalid Access Fault: The process attempted an illegal operation (e.g., writing to a read-only page). The OS typically terminates the process (segmentation fault).

While high-level allocation is managed by the OS, the MMU's paging mechanism provides the hardware foundation for efficient memory use.

• Eliminates External Fragmentation: Physical RAM can be allocated in fixed-size pages (e.g., 4KB). Since all pages are the same size, free pages can be used anywhere, avoiding the "holes" common in older segmentation schemes.
• Supports Large Address Spaces: Allows processes to have a virtual address space larger than the available physical RAM by swapping pages to disk.
• Enables Demand Paging: Pages are only loaded into physical memory when they are actually accessed (on demand), optimizing RAM usage.

Modern MMUs support features essential for performance and advanced system design.

• Huge Pages / Large Pages: Support for larger page sizes (e.g., 2MB, 1GB) to reduce TLB pressure and improve performance for memory-intensive applications like databases.
• Memory Protection Keys: A newer feature providing faster switching of protection domains within a process, useful for sandboxing libraries.
• Nested Paging / Extended Page Tables: Hardware support for virtualization, where the MMU handles two levels of translation (guest virtual -> guest physical -> host physical), reducing hypervisor overhead.
• Speculative Execution Safeguards: Involved in mitigating side-channel attacks like Meltdown and Spectre by enforcing stricter isolation during speculative operations.

A memory management technique that provides an idealized abstraction of the storage resources available to a process. It creates the illusion of a large, contiguous address space by using secondary storage (like an SSD) to extend the apparent size of physical RAM. The MMU is the hardware enabler of this system, translating the process's virtual addresses into actual physical addresses in RAM or triggering a page fault to load data from disk. This allows for efficient multitasking, memory isolation, and the execution of programs larger than available physical memory.

The core data structure used by the MMU and operating system to map virtual addresses to physical addresses. Each entry in the table corresponds to a page (a fixed-size block of memory, e.g., 4KB) and contains:

• The physical frame number.
• Permission bits (read, write, execute).
• Status bits (present, dirty, accessed). The MMU consults the page table on every memory access. To speed this up, it uses a cache called the Translation Lookaside Buffer (TLB). Modern systems use multi-level page tables (e.g., 4-level for 64-bit x86) to manage the vast address space efficiently.

A small, high-speed cache inside the MMU that stores recent virtual-to-physical address translations. Its purpose is to avoid the performance penalty of walking the page table in memory for every address translation. When the CPU issues a virtual address, the MMU first checks the TLB. A TLB hit provides the physical address instantly. A TLB miss forces a slower page table walk, after which the new translation is cached in the TLB. TLBs are critical for performance; their size and organization (fully associative, set-associative) are key CPU design considerations.

A fundamental security and stability mechanism enforced by the MMU. By managing access permissions in the page table entries, the MMU prevents processes from accessing memory they do not own. Key protections include:

• Read/Write/Execute (RWX) Bits: Control the type of access allowed to a memory page (e.g., preventing code execution from a data page).
• User/Supervisor Mode Bit: Restricts access to kernel memory from user-space applications.
• Address Space Layout Randomization (ASLR): Relies on the MMU to randomize the virtual address space of processes, making exploits harder. This hardware-enforced isolation is the bedrock of modern operating system security.

While the MMU manages main memory (RAM), the cache hierarchy sits between the CPU cores and the MMU to bridge the speed gap. It consists of small, fast memory banks:

• L1 Cache: Fastest, smallest, private per core. Split into instruction (L1i) and data (L1d) caches.
• L2 Cache: Larger, slower, often shared between a few cores.
• L3 Cache (LLC): Largest, slowest, shared among all cores on a chip. The MMU's address translation is interwoven with cache access. Virtual caches (e.g., L1) use virtual addresses, while physical caches (e.g., L2/L3) use the physical addresses provided by the MMU, requiring translation before a cache lookup.

A memory architecture for multiprocessor systems where the memory access time depends on the memory location relative to the processor. In a NUMA system, each processor has its own local memory, which it can access quickly. Accessing memory attached to another processor (remote memory) is slower. The MMU and operating system are NUMA-aware, attempting to allocate a process's memory on the local node of the CPU it is running on to minimize latency. This is crucial for performance in modern multi-socket servers and high-core-count CPUs, where memory locality significantly impacts application throughput.