Counterexample-Guided Inductive Synthesis (CEGIS) is an algorithmic loop that iteratively generates candidate programs, verifies them against a formal specification, and uses counterexamples from failed verification to refine subsequent candidates. The core loop consists of a synthesis engine (often an SMT solver or inductive learner) that proposes candidates and a verification engine (a model checker or theorem prover) that either confirms correctness or produces a concrete counterexample input. This counterexample is added to the set of constraints, guiding the next synthesis iteration toward a correct solution.
