Formal verification in program synthesis is the application of mathematical logic and automated theorem proving to guarantee that a synthesized program meets its formal specification, ensuring correctness-by-construction. Unlike testing, which samples behavior, formal verification provides a mathematical proof that the program satisfies its specification for all possible inputs and execution paths. This is typically achieved by encoding the program, its specification, and the synthesis constraints as logical formulas within a framework like Satisfiability Modulo Theories (SMT).
